Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.

Abstract: A method and apparatus for coordinating and authenticating requests for data. In one embodiment, the apparatus comprises: a baseboard management controller (BMC); and a request coordinator coupled to the BMC to intercept BMC requests and to provide intercepted requests to the BMC, where the coordination interface comprises a request parser to parse parameters for each of the BMC requests, one or more queues to store the requests while the BMC is servicing another BMC request, and a command submitter to send individual BMC requests to the BMC, wherein the BMC is operable to generate the responses to the BMC requests received from the coordination interface and to send the responses to the coordination interface.

Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.

Abstract: Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

Abstract: Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device.

Abstract: In some embodiments, an circuit card includes an electronic circuit substrate, a ground plane on the electronic circuit substrate, first and second differential signal pads on the electronic circuit substrate, a ground return signal pad associated with the first and second differential signal pads, the ground return signal pad being connected to the ground plane on the electronic substrate, and a cutout structure on the ground plane positioned near a location where the ground return signal pad connects to the ground plane, wherein the cutout structure is configured to direct a ground return path associated with the first and second differential signal pads to the ground return signal pad associated with the first and second differential signal pads. Other embodiments are disclosed and claimed.