Abstract: A power semiconductor module arrangement includes: a substrate arranged within a housing; at least one semiconductor body arranged on a top surface of the substrate; and a first layer arranged on a first surface within the housing. The first layer includes inorganic filler which is impermeable to corrosive gases and a casting material which fills spaces present in the inorganic filler.

Abstract: A power semiconductor module arrangement includes: a substrate arranged within a housing; at least one semiconductor body arranged on a top surface of the substrate; and a first layer arranged on a first surface within the housing. The first layer includes inorganic filler which is impermeable to corrosive gases and a casting material which fills spaces present in the inorganic filler.

Abstract: A method for producing a power semiconductor module arrangement includes forming a pre-layer by depositing inorganic filler on a first surface within a housing, the inorganic filler being impermeable to corrosive gases. The method further includes filling casting material into the housing to fill spaces present in the inorganic filler of the pre-layer with the casting material, and hardening the casting material to form a first layer.

Abstract: A method for producing a power semiconductor module arrangement includes mixing inorganic fillers with a casting material to prepare a mixture including a first concentration of inorganic fillers, wherein the inorganic fillers have a density that is higher than a density of the casting material. The method further includes filling the mixture into a housing, wherein a semiconductor substrate is arranged within the housing, and wherein at least one semiconductor body is arranged on a top surface of the semiconductor substrate. The method also includes performing a settling step during which the inorganic fillers settle down onto the semiconductor substrate and the at least one semiconductor body to form a first layer including a portion of the casting material and the inorganic fillers, and a second layer including a remaining portion of the casting material without the inorganic fillers. The method also includes hardening the casting material.

Abstract: A method for producing a power semiconductor module arrangement includes forming a pre-layer by depositing inorganic filler on a first surface within a housing, the inorganic filler being impermeable to corrosive gases. The method further includes filling casting material into the housing to fill spaces present in the inorganic filler of the pre-layer with the casting material, and hardening the casting material to form a first layer.

Abstract: A semiconductor chip includes a semiconductor body having a lower side with a lower chip metallization applied thereto. A first contact metallization layer is produced on the lower chip metallization. A second contact metallization layer is produced on a metal surface of a substrate. The semiconductor chip and the substrate are pressed onto one another for a pressing time so that the first and second contact metallization layers bear directly and extensively on one another. During the pressing time, the first contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the first contact metallization layer. The second contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the second contact metallization layer during the pressing time. After the pressing together, the first and second contact metallization layers have a total thickness less than 1000 nm.

Abstract: A semiconductor chip includes a semiconductor body having a lower side with a lower chip metallization applied thereto. A first contact metallization layer is produced on the lower chip metallization. A second contact metallization layer is produced on a metal surface of a substrate. The semiconductor chip and the substrate are pressed onto one another for a pressing time so that the first and second contact metallization layers bear directly and extensively on one another. During the pressing time, the first contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the first contact metallization layer. The second contact metallization layer is kept continuously at temperatures which are lower than the melting temperature of the second contact metallization layer during the pressing time. After the pressing together, the first and second contact metallization layers have a total thickness less than 1000 nm.

Abstract: A layer arrangement in accordance with various embodiments may include: a first layer having a side; one or more nanoholes in the first layer that are open towards the side of the first layer; a second layer filling at least part of the nanoholes and covering at least part of the side of the first layer, the second layer including at least one of the following materials: a metal or metal alloy, a glass material, a polymer material, a ceramic material.

Abstract: A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.

Abstract: A layer arrangement in accordance with various embodiments may include: a first layer having a side; one or more nanoholes in the first layer that are open towards the side of the first layer; a second layer filling at least part of the nanoholes and covering at least part of the side of the first layer, the second layer including at least one of the following materials: a metal or metal alloy, a glass material, a polymer material, a ceramic material.

Abstract: A method for manufacturing a layer arrangement in accordance with various embodiments may include: providing a first layer having a side; forming one or more nanoholes in the first layer that are open towards the side of the first layer; depositing a second layer over the side of the first layer.

Abstract: A semiconductor wafer includes a first main face and a second main face opposite to the first main face and a number of semiconductor chip regions. The wafer is diced along dicing streets to separate the semiconductor chip regions from each other. At least one metal layer is formed on the first main face of each one of the semiconductor chip regions.

Abstract: A method for manufacturing a layer arrangement in accordance with various embodiments may include: providing a first layer having a side; forming one or more nanoholes in the first layer that are open towards the side of the first layer; depositing a second layer over the side of the first layer.