Abstract: Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from the critical path (106), and a window is contracted around the gate (108). Within the window, alternate structures are constructed (110) and sized (112). The best alternative is substituted into the window (114), and the new circuit is resized (116). If the new circuit is not an improvement over the old (118), then the original window is replaced (120). In any case, this is repeated for each gate in the circuit (124). The entire process is then repeated until either user constraints are met, or the circuit doesn't change (122).