Patents by Inventor Gopalan Nair

Gopalan Nair has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210370362
    Abstract: The invention relates to compositions and methods for reducing biocontaminant (for example flesh, blood, mucous, faeces or biofilm) on a surface, such as an endoscope surface. The compositions are viscoelastic and of low lubricity, having the following properties at 21° C.: a rotational yield point between 140% strain and 300% strain; a peak viscosity between 550 Pa·s and 2000 Pa·s; an oscillatory flow point between 250 and 700% strain; and a coefficient of friction ? which has a maximum value (preferably 0.06 or greater) in the viscoelastic liquid's elastohydrodynamic region.
    Type: Application
    Filed: October 16, 2019
    Publication date: December 2, 2021
    Applicant: SABAN VENTURES PTY LIMITED
    Inventors: Alexander GALKIN, Stefan GEBHARDT, Ashwin Gopalan NAIR, Brian HINGLEY, Joshua Storm CALEY
  • Patent number: 7389404
    Abstract: A matrix data processor is implemented wherein data elements are stored in physical registers and mapped to logical registers. After being stored in the logical registers, the data elements are then treated as matrix elements. By using a series of variable matrix parameters to define the size and location of the various matrix source and destination elements, as well as the operation(s) to be performed on the matrices, the performance of digital signal processing operations can be significantly enhanced.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: June 17, 2008
    Assignee: G4 Matrix Technologies, LLC
    Inventors: Gopalan Nair, Archana Sekhar, Prasanth David, Antony Jose
  • Publication number: 20060101245
    Abstract: A matrix data processor is implemented wherein data elements are stored in physical registers and mapped to logical registers. After being stored in the logical registers, the data elements are then treated as matrix elements. By using a series of variable matrix parameters to define the size and location of the various matrix source and destination elements, as well as the operation(s) to be performed on the matrices, the performance of digital signal processing operations can be significantly enhanced.
    Type: Application
    Filed: September 12, 2005
    Publication date: May 11, 2006
    Inventors: Gopalan Nair, Archana Sekhar, Prasanth David, Antony Jose
  • Patent number: 6195733
    Abstract: A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: February 27, 2001
    Assignee: Intel Corporation
    Inventors: N. Gopalan Nair, David Regenold, Parviz Hatami, Ramprasad Satagopan
  • Patent number: 5890013
    Abstract: A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: March 30, 1999
    Assignee: Intel Corporation
    Inventors: N. Gopalan Nair, David Regenold, Parviz Hatami, Ramprasad Satagopan
  • Patent number: 5862491
    Abstract: A method of using control channel information is provided to enhance data throughput of a cellular communication system. The cellular communication system includes a single system control unit coupled to a data pump, a cellular transceiver and a radio transceiver. A method of operating the cellular communication system includes the following steps: (a) detecting a control channel signal indicating that a channel interruption is to occur; (b) decoding the control channel signal; (c) sending the decoded control channel signal to the system control unit; (d) controlling the parameters of the adaptive components of the data pump so that the parameters remain at a converged state or are adjusted even during the channel interruption; (e) interrupting the channel; and (f) re-establishing the channel within a reduced retraining time period.
    Type: Grant
    Filed: October 13, 1997
    Date of Patent: January 19, 1999
    Assignee: Intel Corporation
    Inventors: N. Gopalan Nair, Zdenek A. Brun
  • Patent number: 5696699
    Abstract: A cellular communication system having all of its components operating under a single system control unit is provided so that the various components of the system can be adjusted as the parameters of the other components or the dynamic characteristics of the cellular channel change.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: December 9, 1997
    Assignee: Intel Corporation
    Inventor: N. Gopalan Nair
  • Patent number: 4120953
    Abstract: Novel 2,2', 2"-[s-phenenyltris(sulfonylimino)]tris-[2-deoxy-.alpha.-D-glucopyranose], dodecakis (H-sulfate) compounds and their salts which are useful as inhibitors of the complement system of warm-blooded animals, and the compound 2,2',2"-[s-phenenyltris(sulfonylimino)]tris[2-deoxy-D-glucopyranose] which is a new intermediate for the preparation of the active dodecakis (H-sulfate) compounds.
    Type: Grant
    Filed: April 4, 1977
    Date of Patent: October 17, 1978
    Assignee: American Cyanamid Company
    Inventors: Vijay Gopalan Nair, Seymour Bernstein
  • Patent number: 4098995
    Abstract: Polygalactosido-sucrose Poly(H-)sulfate and salts thereof useful as complement inhibitors.
    Type: Grant
    Filed: July 12, 1976
    Date of Patent: July 4, 1978
    Assignee: American Cyanamid Company
    Inventors: Vijay Gopalan Nair, Joseph Peter Joseph, Seymour Bernstein
  • Patent number: 4066829
    Abstract: Malto-dextrin poly(H-)sulfate and salts thereof useful as inhibitors of the complement system.
    Type: Grant
    Filed: July 12, 1976
    Date of Patent: January 3, 1978
    Assignee: American Cyanamid Company
    Inventors: Vijay Gopalan Nair, Joseph Peter Joseph, Seymour Bernstein
  • Patent number: 4021545
    Abstract: Inulin poly(H-sulfate) and salts thereof useful as complement inhibitors.
    Type: Grant
    Filed: July 12, 1976
    Date of Patent: May 3, 1977
    Assignee: American Cyanamid Company
    Inventors: Vijay Gopalan Nair, Joseph Peter Joseph, Seymour Bernstein
  • Patent number: 4021544
    Abstract: Sulfated oligosaccharides of the maltose series useful as complement inhibitors.
    Type: Grant
    Filed: July 12, 1976
    Date of Patent: May 3, 1977
    Assignee: American Cyanamid Company
    Inventors: Vijay Gopalan Nair, Joseph Peter Joseph, Seymour Bernstein
  • Patent number: D1004400
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: November 14, 2023
    Assignee: US TECHNOLOGY INTERNATIONAL PVT LIMITED
    Inventors: Divyansh Khare, Ashok Gopalan Nair, Rajendra Singh, Sachin Rustagi, Shaik Muhammed Rafi