Abstract: Systems and methods are disclosed for improved processor hang detection. An exemplary method comprises setting a timer with a hang threshold value for each of a plurality of processors of a system on a chip (SoC). The hang threshold value represents a time in microseconds. The method further comprising receiving a first heartbeat signal from each of the plurality of processors with detection logic hardware of a hang controller coupled to the plurality of processors and to the timer. The timer is reset for each of the plurality of processors if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires. Alternatively, a hang event notification is generated if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.