Abstract: A method of low-latency and encrypted hardware layer communication includes calculating, by an encryption circuit of a communication bridge controller, a pre-calculated encryption keys corresponding to a block encryptor of the encryption circuit, each block encryptor configured to use a corresponding pre-calculated encryption key to encrypt a corresponding unencrypted data block of a data transmission having one or more unencrypted data blocks, storing the one or more pre-calculated encryption keys in an encryption key memory associated with the communication bridge, for each unecrypted data block, encrypting the unencrypted data block using the corresponding pre-calculated encryption key to generate an encrypted data block and an authentication code block for the unencrypted data block, aggregating one or more encrypted data blocks into an encrypted data transmission, and generating an authenticated code corresponding to the encrypted data transmission based upon each of the authentication code blocks of eac

Abstract: Embodiments disclosed are directed to methods for scheduling packets. According to example embodiments the method includes receiving, using a first layer in a communication protocol, a first request from a second layer in the communication protocol. The first request indicates to the first layer to output a data stream that includes a first location for the second layer to include a first control packet. The first layer is at a higher level of abstraction than the second layer. The method further includes transmitting, using the first layer, a first response to the second layer. The first response is based on the first request, and the first response identifies the first location in the data stream and a time of occurrence of the first location in the data stream.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

Abstract: One embodiment relates to an integrated circuit configured to perform dynamic transmit equalization of a bi-directional lane. The integrated circuit including an interface between the physical coding and media access control circuitry, and an equalization control circuit which is external to the physical coding circuitry and which is configured to perform the dynamic transmit equalization using said interface. Another embodiment relates to a transceiver circuit which includes physical coding circuitry and media access control circuitry. The transceiver circuit further includes an interface between the physical coding circuitry and the media access control circuitry and an equalization controller which is external to the physical coding circuitry and which is configured to perform dynamic transmit equalization using said interface. The interface is configured to provide transmit coefficient data in a time-multiplexed signal format from the media access control circuitry to the physical coding circuitry.

Abstract: Circuitry for scaling data from a first width (e.g., number of simultaneously presented parallel data signals) to a second width can preferably operate for any of a wide range of different ratios between the first and second widths (including ratios that are non-integer or even non-rational) without the need for more than one clock signal.

Abstract: One embodiment relates to a method for activating an interface on an integrated circuit while a core of the integrated circuit is becoming operational. An offset calibration for a transceiver channel is performed by physical media attachment circuitry. A transmitting frequency is locked onto by a transmitter phase-locked loop for the transceiver channel, and a receiving frequency is locked onto by a receiver phase-locked loop for the transceiver channel. Subsequently, the interface is activated while a core component of the integrated circuit is becoming operational. Another embodiment pertains to an integrated circuit which includes transceiver channel circuits, an interface processor, and a reset control state machine. Another embodiment relates to control circuitry including a reset control state machine, transceiver channel circuits, a channel input steering multiplexer, and a channel output steering multiplexer. Other embodiments, aspects and features are also disclosed.