Patents by Inventor Gopi Neela
Gopi Neela has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240012771Abstract: The described techniques and apparatuses enable memory-request priority up-leveling. A memory request is received over a virtual channel, VC, and is then added to a memory-request buffer with an original priority-level for the memory request and an indication that the memory request is associated with a virtual channel identification, VCID, of the VC. Related memory requests within the memory-request buffer are also indicated as being associated with the VCID. Responsive to determining that an up-level indication for the VCID is asserted over a side channel, the original priority-levels of the memory request, and other memory-requests in the memory-request buffer having an indication of the VCID, are increased to respective up-leveled priority levels. Responsive to determining that the up-level indication is no longer asserted, the up-leveled priority levels are returned to respective original priority-levels.Type: ApplicationFiled: November 5, 2020Publication date: January 11, 2024Applicant: Google LLCInventors: Nagaraj Ashok Putti, Gopi Neela, Shubham Mahajan, Praxal Sunilkumar Shah
-
Publication number: 20230342314Abstract: Techniques and apparatuses are described that enable memory request timeouts using a common counter. A memory request is received, and a common count timeout is generated for the memory request based on a common count at a time of receipt and a latency requirement of the memory request. Common count timeouts of one or more related memory requests within a memory request buffer (if they exist) are adjusted as needed, and the memory request is placed in the memory request buffer. The common count is incremented, and the memory request is indicated as timed out in response to an incrementation of the common count matching the common count timeout for the memory request.Type: ApplicationFiled: September 14, 2020Publication date: October 26, 2023Applicant: Google LLCInventors: Nagaraj Ashok Putti, Vyagrheswarudu Durga Nainala, Gopi Neela, Abhra Bagchi
-
Patent number: 11189000Abstract: An embodiment of an image processor device includes technology to fetch a feature point data set from outside a local memory, locally store three or more fetched feature point data sets in the local memory, compute orientation information for each fetched feature point data set, compute first descriptor information based on the computed orientation information and a first locally stored feature point data set in parallel with a fetch and local store of a second feature point data set in the local memory, and compute second descriptor information based on the computed orientation information and the second locally stored feature point data set in parallel with the compute of the first descriptor information. Other embodiments are disclosed and claimed.Type: GrantFiled: June 24, 2019Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Gopi Neela, Dipan Kumar Mandal, Gurpreet S. Kalsi, Prashant Laddha, Om J. Omer, Anirud Thyagharajan, Srivatsava Jandhyala
-
Publication number: 20190333183Abstract: An embodiment of an image processor device includes technology to fetch a feature point data set from outside a local memory, locally store three or more fetched feature point data sets in the local memory, compute orientation information for each fetched feature point data set, compute first descriptor information based on the computed orientation information and a first locally stored feature point data set in parallel with a fetch and local store of a second feature point data set in the local memory, and compute second descriptor information based on the computed orientation information and the second locally stored feature point data set in parallel with the compute of the first descriptor information. Other embodiments are disclosed and claimed.Type: ApplicationFiled: June 24, 2019Publication date: October 31, 2019Applicant: Intel CorporationInventors: Gopi Neela, Dipan Kumar Mandal, Gurpreet S. Kalsi, Prashant Laddha, Om J. Omer, Anirud Thyagharajan, Srivatsava Jandhyala
-
Patent number: 10324689Abstract: Systems and methods for matrix-solve applications include a memory-optimized hardware acceleration (HWA) solution with scalable architecture (i.e. specialized circuitry) for HWA matrix-solve operations. The matrix-solve solutions described herein may include a scalable hardware architecture with parallel processing (e.g., “within column” processing), which provides the ability to compute several output values in parallel. The HWA matrix-solve solutions described herein may include simultaneous multi-column processing, which provides a lower execution cycle count and a reduced total number of memory accesses. This HWA matrix-solve provides a low latency and energy-efficient matrix-solve solutions, which may be used to reduce energy consumption and improve performance in various matrix-based applications, such as computer vision, SLAM, AR/VR/mixed-reality, machine learning, data analytics, and other matrix-based applications.Type: GrantFiled: November 21, 2017Date of Patent: June 18, 2019Assignee: Intel IP CorporationInventors: Gurpreet Singh Kalsi, Om Ji Omer, Dipan Kumar Mandal, Santhosh Kumar Rethinagiri, Gopi Neela
-
Patent number: 10318834Abstract: One embodiment provides an image processing circuitry. The image processing circuitry includes a feature extraction circuitry and an optimization circuitry. The feature extraction circuitry is to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale. The optimization circuitry is to optimize an operation of the feature extraction circuitry. Each optimization is to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry.Type: GrantFiled: May 1, 2017Date of Patent: June 11, 2019Assignee: Intel CorporationInventors: Gurpreet S. Kalsi, Om J. Omer, Biji George, Gopi Neela, Dipan Kumar Mandal, Sreenivas Subramoney
-
Publication number: 20190042195Abstract: Systems and methods for matrix-solve applications include a memory-optimized hardware acceleration (HWA) solution with scalable architecture (i.e. specialized circuitry) for HWA matrix-solve operations. The matrix-solve solutions described herein may include a scalable hardware architecture with parallel processing (e.g., “within column” processing), which provides the ability to compute several output values in parallel. The HWA matrix-solve solutions described herein may include simultaneous multi-column processing, which provides a lower execution cycle count and a reduced total number of memory accesses. This HWA matrix-solve provides a low latency and energy-efficient matrix-solve solutions, which may be used to reduce energy consumption and improve performance in various matrix-based applications, such as computer vision, SLAM, AR/VR/mixed-reality, machine learning, data analytics, and other matrix-based applications.Type: ApplicationFiled: November 21, 2017Publication date: February 7, 2019Inventors: Gurpreet Singh Kalsi, Om Ji Omer, Dipan Kumar Mandal, Santhosh Kumar Rethinagiri, Gopi Neela
-
Publication number: 20180314903Abstract: One embodiment provides an image processing circuitry. The image processing circuitry includes a feature extraction circuitry and an optimization circuitry. The feature extraction circuitry is to determine a feature descriptor based, at least in part, on a feature point location and a corresponding scale. The optimization circuitry is to optimize an operation of the feature extraction circuitry. Each optimization is to at least one of accelerate the operation of the feature extraction circuitry, reduce a power consumption of the feature extraction circuitry and/or reduce a system memory bandwidth used by the feature extraction circuitry.Type: ApplicationFiled: May 1, 2017Publication date: November 1, 2018Applicant: INTEL CORPORATIONInventors: Gurpreet S. Kalsi, Om J. Omer, Biji George, Gopi Neela, Dipan Kumar Mandal, Sreenivas Subramoney