Abstract: A data storage system includes a bridging device. The bridging device is configured to receive, from a host through a network, a host data block size. A sub-block size is determined based on the host data block size. One or more storage devices are configured to include a plurality of storage sub-blocks each having the sub-block size. A first write command to write first host data including a first number of host data blocks to the one or more storage devices is received. The bridging device compresses the first host data to generate first compressed data, and write the first compressed data to a second number of storage sub-blocks of the one or more storage devices.

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.

Abstract: Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.

Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.

Abstract: Method and apparatus for discovery of operational boundaries for shmoo tests. Specifically, a method of testing operational boundaries is described in one embodiment of the present invention. The method discloses the discovery of an operational range for a hardware device over a plurality of varying operating parameters. The operational range is discovered by testing points, as defined by the plurality of varying operating parameters, to discover an operational boundary of the device. The operational boundary comprises a plurality of boundary points that lie just outside of the operational range of the device. The operational boundary is discovered automatically and without testing all of a plurality of interior operational points within the operational boundary.

Abstract: Method and apparatus for discovery of operational boundaries for shmoo tests. Specifically, a method of testing operational boundaries is described in one embodiment of the present invention. The method discloses the discovery of an operational range for a hardware device over a plurality of varying operating parameters. The operational range is discovered by testing points, as defined by the plurality of varying operating parameters, to discover an operational boundary of the device. The operational boundary comprises a plurality of boundary points that lie just outside of the operational range of the device. The operational boundary is discovered automatically and without testing all of a plurality of interior operational points within the operational boundary.