Abstract: In a digital phase-locked loop, preferably for bit rate regeneration in synchronous data transmission systems, transmitting from a sender to a receiver redundantly coded information possibly modulated in a suitable mode there is an addition circuit connected to one control input of a digital controlled oscillator incorporated in the loop. The addition circuit adds control signal contributions from a phase comparator circuit of the loop and an error detector. This error detector is connected to an output of the receiver data detector, and examines whether the input signal in the circuit has the inherent redundant properties expected taking into account the signal coding. When this is not the case, a pulse-shaped control signal is fed to the addition circuit.

Abstract: A method and an apparatus for phase synchronization in a synchronous data transmission system, which transmits a binary pulse train from a transmitter to a receiver by means of an amplitude-modulated carrier. The modulation is of the so-called single-side band type (SSBAM) and the modulating signal which has been derived from the input data flow consists of superimposed pulses of so-called Partial-Response Class 4 type. The receiver clock generator consists of a digital phase-locked loop (TK, FD) controlled by level crossovers in the baseband signal, in which there is arranged between the phase detector (FD) and the oscillator (TK) a sorting circuit (SD), which sorts out and passes through to the oscillator (TK) only such information related to detected level crossovers of a predetermined first category. Further, carrier regeneration is provided by a second phase-locked loop (CR) in series with a phase correction circuit (FK).