Abstract: A MacBeth color checker chart automatic detection system includes an imaging unit that provides an image and a processing unit that applies an edge detection operation to the image and performs a flood-fill operation on the image to provide a flood-filled image. Additionally, the MacBeth color checker chart automatic detection system includes a testing unit that tests the flood-filled image to provide a modified flood-fill image, wherein a set of heuristic tests are employed to automatically determine quantity and location of MacBeth color checker charts. Generally, the set of heuristic tests are employed to automatically reject regions that are unlikely to belong to a MacBeth color checker chart and to cluster the remaining regions that are likely to belong to a Macbeth color checker chart. A MacBeth color checker chart automatic detection method is also provided.

Abstract: A MacBeth color checker chart automatic detection system includes an imaging unit that provides an image and a processing unit that applies an edge detection operation to the image and performs a flood-fill operation on the image to provide a flood-filled image. Additionally, the MacBeth color checker chart automatic detection system includes a testing unit that tests the flood-filled image to provide a modified flood-fill image, wherein a set of heuristic tests are employed to automatically determine quantity and location of MacBeth color checker charts. Generally, the set of heuristic tests are employed to automatically reject regions that are unlikely to belong to a MacBeth color checker chart and to cluster the remaining regions that are likely to belong to a Macbeth color checker chart. A MacBeth color checker chart automatic detection method is also provided.

Abstract: A computer implemented method for utilizing graphics memory of a computer system to provide storage for video BIOS initialization. Video BIOS memory is accessed to execute video BIOS initialization routines. A portion of graphics memory is configured for access by the video BIOS initialization routines. Program execution data from the video BIOS initialization routines is then stored in the portion of graphics memory. The program execution data is stored prior to a completion of a video BIOS power on self test.

Abstract: A method and system for performing enhanced lighting functions with respect to texture map data is operable within a computer controlled graphics display system and allows defined portions of a texture map to bypass prescribed lighting processes. Within a texture map, each texel data (u,v) is defined to contain color information and a control code (e.g., “texel light bit”). The texel light bit indicates to the lighting process whether or not texel color modulation is to occur to this texel data. In one embodiment, if the texel light bit is set, then no lighting modifications (e.g., color modulations) are performed with respect to the texel data. Also, if the texel light bit is not set, then normal lighting modifications are performed with respect to the texel data. In this way, the present invention allows texture map data to be lit in a non-uniform manner across a same graphics primitive. The present invention is particularly useful with respect to graphics objects (e.g.

Abstract: A graphics processor is disclosed that renders polygons with specular highlighting (glare) based on specular fractional values included in a texture map as components of each texel in the texure map. Each texel in the texture map includes red, green, and blue color values and the specular fractional component. The specular fractional component determines the proportion or percentage of a specular color value that is to be combined with the texel color values. The graphics processor preferably comprises a texture map engine that includes multiplier logic and adder logic. The texture map engine receives three values preferably from a video memory device—the texel color value, the specular fractional component value, and the specular color value. The multiplier multiplies the specular fraction by the specular color value and the resulting product is added to the texel color value. The output value from the adder is then used to render a screen pixel or is provided to another lighting stage.

Abstract: A method and system for filtering texture map data for improved image quality in a graphics computer system. The present invention is directed to a method and system for performing texture map filtering for reducing “flickering” and “sparkling” when rendering a relatively small graphics primitives using a texel map of relatively larger area and low color frequency. A footprint area is defined as the area of texel map space that is mapped into one pixel coordinate of display space. One embodiment of the present invention is particularly useful in texture mapping where the footprint area is larger than one. In this instance, during rendering, the change in texel map coordinates (e.g., du, dv) is large for a unit change in screen coordinates (e.g., dx, dy). When obtaining a texel at location (u, v), the present invention performs a color filtering of texels located at distances du and dv away from the texel at location (u, v).

Abstract: A graphics system including a selectable mode smoothing filter for improved texture mapping. An x, y pixel coordinate is mapped into a u, v texture map. The mapped u, v coordinate includes integer and fractional portions. Depending on the location of the coordinate relative to the four nearest texels, which are represented as integers, one of several texture mapping schemes are used to either select or calculate the texel value to be used to render the pixel at the x, y screen location. The three texture mapping schemes include point sampling in which the nearest texel from the texture map is selected, two-texel averaging in which the closest two texels are combined in a weighted average, and four-texel averaging in which the closest four texels are combined in a weighted average. Scale factors in the range of 0 to 1 are computed for averaging texel values together.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a shortened display list. A host processor generates a display list which includes a field load instruction for loading the display list into a register file. The graphics processor includes logic to encode and decode the field load instruction thereby shortening the display list loaded into the register file. The field load instruction may also be decoded to allow the graphics processor to randomly load the register file thereby shortening the processing of the display list.

Abstract: A graphics system includes a graphics controller for rendering polygons with specular highlighting (glare) based on a comparison of texel color values from a texture map to a range of color values. The graphics processor includes range registers for storing the range of color values and color comparators for comparing a texel color value to the range of colors stored in the range registers. The range of color values used in the comparison corresponds to the range of colors of those portions of a texture for which specular highlighting is appropriate, such as metallic surfaces off which light reflects. If a texel color value to be applied to a screen pixel is within the range of colors defined for specular highlighting, the graphics processor adds an appropriate specular component to the texel value.

Abstract: In a computer system, a peripheral graphics device (PGD) accesses a graphics buffer (GB) wherein the GB physical pages can be contiguous or discontiguous. A request is received to allocate memory for a GB of a predetermined size and handle. The number of pages within the size parameter is determined based on the page size used by the computer system and the buffer size needed. A first memory block is allocated for storing the GB and locked to prevent swapping. A starting virtual address of a CPU page table (CPU/PT) is accessed and mapped to a starting logical address to allow traversal of the CPU/PT by a user application. A second memory block is allocated for building a graphics device page table (GDPT) that can be accessed by a PGD. The logical address of each GB page is sequentially accessed and the corresponding physical address of each GB page is determined from the CPU/PT. The logical and physical addresses of each GB page are stored into the GDPT.

Abstract: A method and apparatus that adjusts certain graphics processing procedures based on a selectable speed/quality (S/Q) adjustment gauge. The S/Q adjustment can be tuned within a predetermined range (e.g., 0 to 255) where on one side, speed is represented over image quality while on the other side, image quality is represented over speed. Settings between the ends give proportional representation for speed and quality. A first graphics process determines whether linear or perspective texture mapping processes are to be used on the selected polygon based on: 1) the size of the polygon measured against a predetermined size threshold; and 2) the relative perspective of the polygon measured against a perspective threshold. The S/Q setting alters these thresholds to alter the operation of the first graphics procedure. A second graphics process splits a selected polygon graphics primitive based on the relative perspective of the polygon compared to a predetermined perspective threshold.

Abstract: In a computer controlled graphics system, processes are provided for detecting errors incurred in a display list having variable length instruction/parameter (I/P) sets, the errors occurring during parameterization, transmission, branching, and storage of the display list. Each process includes generating a display list including I/P sets, each I/P set including n parameter words following an instruction word. In each embodiment, a display list is encoded, transmitted, stored in a memory unit, and verified. In one embodiment, the display list is encoded by storing into each instruction word of each I/P set a parity bit of a value representative of the parity of the whole I/P set. In another embodiment, the display list is encoded by storing within each instruction word of each I/P set an m-bit checksum value. The m-bit checksum value is generated by partitioning each I/P set into y m-bit partitions which are summed, ignoring overflow.

Abstract: A computer graphics display system and method are described for rendering objects formed of at least one geometric primitive as pixel images which collide or intersect in three dimensional space. A depth buffer stores depth information representing graphics images rendered by the graphics system. Data stored in the depth buffer representing graphics objects displayed in the three dimensional space are partitioned into three portions comprising an identification portion to store information identifying each object rendered in the three dimensional space, an object resolution portion to store data for controlling the resolution of the graphics object on a display screen, and a depth coordinate portion for storing the coordination information of the object rendered in the three dimensional space. A collision detection is provided to detect and determine when two objects collide on the display screen.

Abstract: A low level hardware dependent graphics library (binding library) between hardware independent graphics libraries and a graphics hardware unit. The binding library procedures provide a relatively low level interface that couples directly with the graphics hardware unit and only requires a relatively small amount of rewriting to accommodate different graphics hardware units while requiring no change of the hardware independent graphics libraries. The binding library procedures provide a quality meter adjustable between low speed processing high quality image rendering and low quality but faster speed image rendering. The binding library procedures perform batch processing by receiving an array of batch cells, each batch cell comprising a separate primitive. The batch array can be handed off to the binding library procedures at one setting and then processed sequentially. This configuration insures that no instruction cache misses occur during parameterization of the array (e.g.