Abstract: A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.

Abstract: A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.

Abstract: A device includes a transmitter configured to obtain a particular set of bit values to be sent via a set of wires of a communication link. The transmitter is also configured to determine, based on a transition pattern associated with the particular set of bit values, whether to send the particular set of bit values during a single transmission period or during multiple transmission periods. The transmitter is further configured to send the particular set of bit values based on the determination.

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

Abstract: Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.