Abstract: Instant optical DRAM data erasure can be performed. In wafer level packaging (chip scale package) die is usually on top (flip-chip) and metal interconnections does not interfere with penetrating light during chip illumination. IR light penetrates through chip's thin epoxy on top and deeply into die. Light is absorbed in the die, near active layer, generating electron-hole pairs. Electron-hole pairs diffuse to chip active layer and generate discharging photocurrents in DRAM capacitors.

Abstract: Instant optical DRAM data erasure can be performed. In wafer level packaging (chip scale package) die is usually on top (flip-chip) and metaliterconnections does not interfere with penetrating light during chip illumination. IR light penetrates through chip's thin epoxy on top and deeply into die. Light is absorbed in the die, near active layer, generating electron-hole pairs. Electron-hole pairs diffuse to chip active layer and generate discharging photocurrents in DRAM capacitors.

Abstract: Quick optical DRAM reset and data erasure can be performed during power down (power cycling) or chip cooling and removal from the socket. In this way cold boot attacks on DRAM secret information are prevented using simple and cheap embodiment. In wafer level packaging (chip scale package) die is usually on top (flip-chip) and metal interconnections does not interfere with penetrating light during chip illumination. IR light penetrates through chip's thin epoxy on top and it is absorbed in the die, near active layer, and generates electron-hole pairs. Electron-hole pairs diffuse to chip active layer and generate discharging photocurrents in PN junctions connected to DRAM capacitors.

Abstract: Quick optical DRAM reset and data erasure can be performed during power down (power cycling) or chip cooling and removal from the socket. In this way cold boot attacks on DRAM secret information are prevented using simple and cheap embodiment. In wafer level packaging (chip scale package) die is usually on top (flip-chip) and metal interconnections does not interfere with penetrating light during chip illumination. IR light penetrates through chip's thin epoxy on top and it is absorbed in the die, near active layer, and generates electron-hole pairs. Electron-hole pairs diffuse to chip active layer and generate discharging photocurrents in PN junctions connected to DRAM capacitors.

Abstract: A method for refreshing static random access memory comprises providing at least one six-transistor static random access memory cell disposed on a substrate and providing a light source emitting light. The six-transistor static random access memory cell comprises two storage nodes, two pass transistors, two load transistors, and two driver transistors, the drain diffusion regions of the load transistors forming pn-junctions with the substrate. A portion of the light emitted by the light source is absorbed and converted to minority carriers in the substrate, The minority carriers diffuse through the substrate, and a portion of the minority carriers reach the pn-junctions and cause the pn-junctions to generate electrical current. The electrical current generated charges the storage nodes.

Abstract: If the power of SRAM is completely switched off including substrate and wells or more precisely if power supply rails are put on ground potential, leakage is non existing but the data is lost. It is however possible that data is retained in power off mode under optical illumination of substrate where parasitic photodiodes connected to charge nodes are operating in photovoltaic mode. Power for data retention is generated by light and there is no power consumption from power supply which is essential for mobile battery operated devices.

Abstract: A method for refreshing static random access memory comprises providing at least one six-transistor static random access memory cell disposed on a substrate and providing a light source emitting light. The six-transistor static random access memory cell comprises two storage nodes, two pass transistors, two load transistors, and two driver transistors, the drain diffusion regions of the load transistors forming pn-junctions with the substrate. A portion of the light emitted by the light source is absorbed and converted to minority carriers in the substrate, The minority carriers diffuse through the substrate, and a portion of the minority carriers reach the pn-junctions and cause the pn-junctions to generate electrical current. The electrical current generated charges the storage nodes.

Abstract: Loadless 4 transistor SRAM cell operation can be substantially improved, yielding area saving and more stable operation by use of optical-light load. Parasitic photocurrents in PMOS anodes-substrate junctions act as load currents. Light can be introduced by either ambient light through transparent window on top of the chip or by cheap LED diode attached to chip surface.

Abstract: Loadless 4 transistor SRAM cell operation can be substantially improved yielding area saving and more stable operation by use of optical-light load. Parasitic photocurrents in PMOS anodes-substrate junctions act as load currents. Light can be introduced by either ambient light through transparent window on top of the chip or by cheap LED diode attached to chip surface.

Abstract: A single ended three transistor quasi-static RAM cell comprises two cross coupled MOS transistors and one select MOS transistor connected to drain of one of the aforementioned MOS transistors wherein drains of both cross coupled MOS transistors are each connected to anode of one of two PN diodes functioning as constant current loads when exposed to continuous light from LED diode.

Abstract: A self-refreshing dynamic memory cell comprises a first MOSFET and a first capacitor forming a classical dynamic memory cell, a first diode connected with the power supply and the first capacitor, which is under small reverse voltage when the first capacitor is slightly discharged due to a leakage currently and in which reverse current compensates leakage current since it flows in opposite direction, together with additional circuit means which compensates unwanted reverse current through the first diode when the first capacitor is coupled to a positive voltage through the first MOSFET and which tends to charge the first capacitor and change the stored data.

Abstract: A memory device employing optoelectronic elements which in combination form a dynamic RAM, the elements comprising first and second photodiodes electrically connected for exchange of a reverse bias condition from one photodiode to the other when either one is exposed to light to cause a photocurrent to flow, thereby to define logical `0` and `1` states, and an optical switch such as a MOS structure connected in parallel with one of the photodiodes so as to be rendered light transmissive in only one of the reverse bias conditions, thereby to detect the logical state of the cell when exposed to incident light.