Patents by Inventor Gorden Seth Starkey, Jr.

Gorden Seth Starkey, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vertical DRAM cell with TFT over trench capacitor
    Patent number: 6373091
    Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: April 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: David Vaclav Horak, Rick Lawrence Mohler, Gorden Seth Starkey, Jr.
  • Vertical DRAM cell with TFT over trench capacitor
    Patent number: 6228706
    Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: May 8, 2001
    Assignee: International Business Machines Corporation
    Inventors: David Vaclav Horak, Rick Lawrence Mohler, Gorden Seth Starkey, Jr.