Abstract: A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz.

Abstract: A PLL circuit (1a, 1b) for generating a pixel-clock signal based on a hsync signal. The PLL circuit comprises a phase-frequency detector arranged to receive the hsync signal and a frequency divided pixel-clock signal, and generate up and down signals based on the hsync signal and the frequency-divided pixel-clock signal. A charge pump (20) is arranged to generate an output signal based on the up and down signals and a loop filter (30) is arranged to generate a frequency-control signal based on the output signal of the charge pump (20). Furthermore, a VCO (40a, 40b) is arranged to generate an oscillating signal and adjust the frequency of the oscillating signal in response to the frequency-control signal. The VCO (40a, 40b) is adapted to have a tuning range with a center frequency which is larger than or equal to 4 GHz.

Abstract: In order to facilitate its construction as in integrated circuit, the inductive elements of two resonant circuits in a band-pass filter are each constituted by a first port of a respective gyrator circuit (22, 23 and 24, 25 respectively) the second port of which is loaded by a capacitor (3 and 6 respectively). The first ports, across which are connected capacitors (1 and 3 respectively), are connected by a signal path one to the other, as are the second ports, in such manner that a loop is formed comprising the two gyrator circuits and the two signal paths, enabling bilateral coupling of the two gyrator circuits to be obtained by coupling otherwise unused outputs (24+ and 22+) to otherwise unused inputs (22- and 24- respectively) of two-input two-output voltage-controlled current sources (22, 24) which form part of each gyrator circuit.

Abstract: In a filter circuit a reactance is simulated by a voltage amplifier the input of which is connected across a reactive element and the output of which is connected in series with that element, thereby enabling, for example, the series arrangement of a pair of inductances to be simulated by a single capacitively-loaded gyrator (15, 16, 7) and a voltage amplifier (15, 8). The circuit shown simulates a series-resonant circuit fed via a series inductor and is suitable for use as a sound trap in a television receiver. A current proportional to the voltage across the unloaded port (8) of the gyrator (15, 16) generates a corresponding voltage across a load resistor (12) and this voltage is injected effectively in series with any voltage present across a pair of input terminals (1, 2) by means of a differential voltage amplifier (13).