Abstract: A system for providing synchronous access to hardware resources includes a first network interface element to receive a network time signal from a data communication network and a memory to store sequence of one or more instructions selected from an instruction set of the first processing circuit. The sequence of one or more instructions include a first instruction that is configured to synchronize execution of a second instruction of the sequence of one or more instructions with the network time signal. The system further includes a first processing circuit to use the first instruction and a timing parameter associated with a second instruction to execute the second instruction in synchrony with the network time signal.

Abstract: A battery system monitor includes cell measurement circuits (CMCs) that each measure a voltage at or current through a pair of terminals of a respective associated battery module from among a plurality of plurality of battery modules in a battery system. Wireless communication transceivers (WCTs), each associated with a different CMC, transmit voltage or current measurement information of the associated CMC across a wireless communication link. A controller receives the voltage or current measurement information from the wireless communication transceivers for monitoring the state of operation of the battery system. Battery system monitoring is improved through synchronization of clocks in different CMCs or WCTs to enable synchronous sampling of multiple battery modules, through systems for determining relative positions of battery modules in a series coupling of battery modules between terminals of the battery system, and through improvements to the reliability of wireless communication.

Abstract: A system for synchronizing nodes in a wireless network comprises a first node and a second node. The first node comprising a transmitter, a receiver, and a first time keeper. The second node comprising a transmitter, a receiver, a second time keeper, a timing error measurer for making a timing error measurement between the first time keeper and the second time keeper. The second timekeeper is adjusted to target minimizing the timing error measurement.

Abstract: A precision temperature sensing system includes a heater and a sensing element disposed on a semiconductor substrate. A power source drives the heater on a periodic basis according to a received clock signal. The sensing element senses the heat emitted by the heater and diffused through the semiconductor substrate. Processing circuitry coupled to the sensing element adjusts a phase of the periodic heater driving signal based on the heat sensed by the sensing element. The processing circuitry determines a temperature based on a thermal diffusivity (TD) of the semiconductor substrate, the adjusted value of the phase, and a known distance between the heater and the sensing element. A second temperature sensor can be disposed on the same substrate as the precision temperature sensing system, and calibrated based on temperature measurements obtained while applying a reference frequency signal to the precision sensing system.

Abstract: A system for synchronizing nodes in a wireless network comprises a first node and a second node. The first node comprising a transmitter, a receiver, and a first time keeper. The second node comprising a transmitter, a receiver, a second time keeper, a timing error measurer for making a timing error measurement between the first time keeper and the second time keeper. The second timekeeper is adjusted to target minimizing the timing error measurement.

Abstract: A system for synchronizing nodes in a wireless network comprises a first node and a second node. The first node comprising a transmitter, a receiver, and a first time keeper. The second node comprising a transmitter, a receiver, a second time keeper, a timing error measurer for making a timing error measurement between the first time keeper and the second time keeper. The second timekeeper is adjusted to target minimizing the timing error measurement.

Abstract: The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure.

Abstract: A precision temperature sensing system includes a heater and a sensing element disposed on a semiconductor substrate. A power source drives the heater on a periodic basis according to a received clock signal. The sensing element senses the heat emitted by the heater and diffused through the semiconductor substrate. Processing circuitry coupled to the sensing element adjusts a phase of the periodic heater driving signal based on the heat sensed by the sensing element. The processing circuitry determines a temperature based on a thermal diffusivity (TD) of the semiconductor substrate, the adjusted value of the phase, and a known distance between the heater and the sensing element. A second temperature sensor can be disposed on the same substrate as the precision temperature sensing system, and calibrated based on temperature measurements obtained while applying a reference frequency signal to the precision sensing system.

Abstract: A system for maintaining synchronization of nodes in a wireless network comprises a child node and a parent node. The child node comprising a transmitter, a receiver, and a first time keeper. The parent node comprising a transmitter, a receiver, a second time keeper. The parent node receiver is active for a guardband and wherein the guardband is adjusted to maintain synchronization of the parent node with the child node.

Abstract: The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure.