Abstract: An electronic component mounting structure, manufacturing method and an electronic component product are provided. The electronic component mounting structure comprises a printed circuit board, a metal flange, and a plurality of electronic components provided on the metal flange; a groove is provided on the printed circuit board, a metal layer is coated on a wall of the groove, the metal flange is restricted to the metal layer on the wall and is fixed in the groove, the one or more electronic components are connected to each other through a plurality of wires based on a circuit requirement, an input electrode and an output electrode are provided on the printed circuit board in a portion adjacent to the metal flange, and the input electrode and the output electrode are connected to the one or more electronic components mounted on the metal flange through wires respectively.

Abstract: An electronic component mounting structure, manufacturing method and an electronic component product are provided. The electronic component mounting structure comprises a printed circuit board, a metal flange, and a plurality of electronic components provided on the metal flange; a groove is provided on the printed circuit board, a metal layer is coated on a wall of the groove, the metal flange is restricted to the metal layer on the wall and is fixed in the groove, the one or more electronic components are connected to each other through a plurality of wires based on a circuit requirement, an input electrode and an output electrode are provided on the printed circuit board in a portion adjacent to the metal flange, and the input electrode and the output electrode are connected to the one or more electronic components mounted on the metal flange through wires respectively.

Abstract: Conventional broadband RF power amplifiers use a ¼ wavelength transmission line to decouple the gate bias DC source from the gate circuitry and a second ¼ wavelength transmission line to decouple the drain bias DC source from the drain circuitry, taking up considerable printed circuit board space. A novel broadband RF power amplifier uses a transistor with separate terminals for injection of gate bias and drain bias DC sources, eliminating the need for ¼ wavelength transmission lines, thereby freeing up space and allowing higher density packaging. The power amplifier transistor can be implemented with a single die circuit or multiple die circuits operating in parallel.

Abstract: A method of manufacturing a semiconductor component includes sequentially disposing a first electrically conductive layer (130), a dielectric layer (140), and a sacrificial layer (150) over a substrate (110). An etch mask is used to defined a gate stack (210) comprised of the sacrificial layer (150), the dielectric layer, and the first electrically conductive layer. Another dielectric layer (310) is deposited over the substrate (110) and the gate stack (210). This second dielectric layer (310) is planarized to expose the sacrificial layer (150). The sacrificial layer (150) of the gate stack (210) and the dielectric layer (140) of the gate stack (210) are sequentially removed, and another electrically conductive layer (740) is deposited over the first electrically conductive layer of the gate stack to form a gate electrode made of, among other features, two electrically conductive layers.

Abstract: A semiconductor component includes a substrate (101), an electrode (105) located over the substrate (101), a heavily doped region (542) located in the substrate (101) and self-aligned to the electrode (105), an other heavily doped region (543) located in the substrate (101), a lightly doped region (422) located in the substrate (101) between the heavily doped regions (542, 543) and self-aligned to the electrode (105), and another lightly doped region (432) located in the substrate (101) between the lightly doped region (422) and the other heavily doped region (543).

Abstract: An NMOS transistor has a source and a drain composed of n+ type of semiconductor material. A substrate region composed of a p type of semiconductor material is disposed between the source and the drain. A gate region is disposed above the substrate region and between the source region and the drain region. A first implant region is disposed adjacent to the source region and the gate region. The first implant region is composed of p type of semiconductor material with a first doping concentration. A second implant region is disposed between the first implant region and the substrate. The second implant region is composed of p type of semiconductor material with a second doping concentration. The channel doping profile first and second implant regions is tailored to obtain the optimum internal electric field to maximize device transconductance, while simultaneously controlling the device threshold voltage and punch through characteristics.