Abstract: A computer system retrieves a slice of sparse matrix data, which includes multiple rows that each includes multiple elements. The computer system identifies one or more non-zero values stored in one or more of the rows. Each identified non-zero value corresponds to a different row, and also corresponds to an element location within the corresponding row. In turn, the computer system stores each of the identified non-zero values and corresponding element locations within a packet at predefined fields corresponding to the different rows.

Abstract: A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly.

Abstract: A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly.

Abstract: A computer system retrieves a slice of sparse matrix data, which includes multiple rows that each includes multiple elements. The computer system identifies one or more non-zero values stored in one or more of the rows. Each identified non-zero value corresponds to a different row, and also corresponds to an element location within the corresponding row. In turn, the computer system stores each of the identified non-zero values and corresponding element locations within a packet at predefined fields corresponding to the different rows.

Abstract: A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly.

Abstract: A computer system retrieves a slice of sparse matrix data, which includes multiple rows that each includes multiple elements. The computer system identifies one or more non-zero values stored in one or more of the rows. Each identified non-zero value corresponds to a different row, and also corresponds to an element location within the corresponding row. In turn, the computer system stores each of the identified non-zero values and corresponding element locations within a packet at predefined fields corresponding to the different rows.

Abstract: A computer system retrieves a slice of sparse matrix data, which includes multiple rows that each includes multiple elements. The computer system identifies one or more non-zero values stored in one or more of the rows. Each identified non-zero value corresponds to a different row, and also corresponds to an element location within the corresponding row. In turn, the computer system stores each of the identified non-zero values and corresponding element locations within a packet at predefined fields corresponding to the different rows.

Abstract: A computer system retrieves a packet that includes non-zero elements that correspond to sparse-matrix rows. Within the packet, the non-zero elements are stored in predefined fields that each correspond to one of the sparse-matrix rows. The computer system computes output values to correspond with each of the sparse-matrix rows using the non-zero elements and corresponding input values. In turn, the computer system stores the computed output values in consecutive locations within an output buffer and processes the output values accordingly.

Abstract: A method, apparatus, and computer implemented instructions for generating antialiased lines for display in a data processing system. Graphics data is received for display, wherein the graphics data includes primitives defining lines. A gamma correction is applied to the graphics data on a per primitive basis to form antialiased lines. The antialiased lines are displayed.

Abstract: A system and method for cache optimized data formatting is presented. A processor generates images by calculating a plurality of image point values using height data, color data, and normal data. Normal data is computed for a particular image point using pixel data adjacent to the image point. The computed normalized data, along with corresponding height data and color data, are included in a limited space data stream and sent to a processor to generate an image. The normalized data may be computed using adjacent pixel data at any time prior to inserting the normalized data in the limited space data stream.

Abstract: An image is generated that includes ray traced pixel data and rasterized pixel data. A synergistic processing unit (SPU) uses a rendering algorithm to generate ray traced data for objects that require high-quality image rendering. The ray traced data is fragmented, whereby each fragment includes a ray traced pixel depth value and a ray traced pixel color value. A rasterizer compares ray traced pixel depth values to corresponding rasterized pixel depth values, and overwrites ray traced pixel data with rasterized pixel data when the corresponding rasterized fragment is “closer” to a viewing point, which results in composite data. A display subsystem uses the resultant composite data to generate an image on a user's display.

Abstract: A system and product for a DMA controller with multi-dimensional line-walking functionality is presented. A processor includes an intelligent DMA controller, which loads a line description that corresponds to a shape or line. The intelligent DMA controller moves through a memory map and retrieves data based upon the line description that includes a major step and a minor step. In turn, the intelligent DMA controller retrieves data from the shared memory without assistance from its corresponding processor. In one embodiment, the intelligent DMA controller may analyze a line using the rate of change along its minor axes in conjunction with locations where the line intersects subspaces and store array spans of contiguous memory along the line's major axis.

Abstract: An approach to optimize specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process. In one embodiment, the invention may be implemented using PowerPC™ assembly and VMX™ or Altivec™ instructions. In this embodiment, the intensity instruction may be represented as a “vspecefp” instruction, which stands for a “vector specular estimate floating point” instruction.

Abstract: Adaptive span computation when ray casting is presented. A processor uses start point fractional values during view screen segment computations that start a view screen segment's computations a particular distance away from a down point. This prevents an excessive sampling density during image generation without wasting processor resources. The processor identifies a start point fractional value for each view screen segment based upon each view screen segment's identifier, and computes a view screen segment start point for each view screen segment using the start point fractional value. View screen segment start points are “tiered” and are a particular distance away from the down point. This stops the view screen segments from converging to a point of severe over sampling while, at the same time, providing a pseudo-uniform sampling density.

Abstract: A sampling module that adjusts the sampling density of a static data set. Two or more rays are cast onto a surface from a single point of origin. The ray or rays intersect the surface at various locations. The distance between the intersection points of each pair of adjacent rays is calculated. This distance is the current sample density. The current sample density is compared to the desired sample density. If the current sample density is not equal to the desired sample density then the sample density of the next casting of rays is adjusted accordingly.

Abstract: An image is generated that includes ray traced pixel data and rasterized pixel data. A synergistic processing unit (SPU) uses a rendering algorithm to generate ray traced data for objects that require high-quality image rendering. The ray traced data is fragmented, whereby each fragment includes a ray traced pixel depth value and a ray traced pixel color value. A rasterizer compares ray traced pixel depth values to corresponding rasterized pixel depth values, and overwrites ray traced pixel data with rasterized pixel data when the corresponding rasterized fragment is “closer” to a viewing point, which results in composite data. A display subsystem uses the resultant composite data to generate an image on a user's display.

Abstract: A method for optimized specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process.

Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.

Abstract: An image that includes ray traced pixel data and rasterized pixel data is generated. A synergistic processing unit (SPU) uses a rendering algorithm to generate ray traced data for objects that require high-quality image rendering. The ray traced data is fragmented, whereby each fragment includes a ray traced pixel depth value and a ray traced pixel color value. A rasterizer compares ray traced pixel depth values to corresponding rasterized pixel depth values, and overwrites ray traced pixel data with rasterized pixel data when the corresponding rasterized fragment is “closer” to a viewing point, which results in composite data. A display subsystem uses the resultant composite data to generate an image on a user's display.

Abstract: High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.