Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: A neuromodulation therapy is delivered via at least one electrode implanted subcutaneously and superficially to a fascia layer superficial to a nerve of a patient. In one example, an implantable medical device is deployed along a superficial surface of a deep fascia tissue layer superficial to a nerve of a patient. Electrical stimulation energy is delivered to the nerve through the deep fascia tissue layer via implantable medical device electrodes.

Abstract: When an automatic circuit tester (10) detects that a fault has occurred in a circuit board (14), it applies to the circuit board (14) a sequence of vectors that differs from the test sequence (T.sub.n, T.sub.n+1) by which the fault detection occurs only in that each vector's component that corresponds to an input pin in question on the board device under test maintains a level that simulates an open circuit at that input pin. If the resultant response differs from the response to the original test sequence, the input pin can often be ruled out as one at which a fault has occurred. In this way, many open-circuit faults at input pins can be diagnosed without special probing, even when several such faults occur simultaneously.

Abstract: A method of performing in-circuit testing of interior points of circuit boards containing both boundary-scan and non-scan components that utilizes the boundary-scan facility. The testing procedure involves isolation of the non-scan components and either driving or sensing voltages at physically accessible test sites. The method permits use of isolation and multiplexing solutions that are ordinarily developed for in-circuit testing of board components, resulting in efficient design and implementation of interconnect tests.

Abstract: An improved logic simulation system including a logic simulator which provides the logic states of elements within an electronic circuit being analyzed, means for associating the logic states with a schematic image of the electronic circuitry for display on a visual display device, wherein the improvement includes means for designating the color of the element being displayed which color represents the logic state of the element for a selected point in time.

Abstract: In a system for generating tests for digital circuits, a fault simulator (16) simulates a fault-free version of the circuit and all expected faulty versions of it concurrently, basing its operation on information contained in a data base (12) that contains information about the structure and possible defects of the circuits to be tested. A waveform system (14) carries high-level information regarding the general structure of the test waveform that ultimately is to be derived, such as clock signals, timing constraints, and other restrictions that the designer of the circuit under test has placed on the signals to be applied to it.