Abstract: A large scale integrated (LSI) array of standard cells arranged in rows and columns adapted to receive different metallization patterns for producing custom circuits. Disposed in one half of each cell is a first power contact and contacts for the sources, drains and gates of field effect transistors of one conductivity type. Disposed in the other half of each cell is a second power contact and contacts for the sources, drains and gates of field effect transistors of complementary conductivity type. The pattern formed by the contacts in one half of a cell is the mirror image of the pattern formed by the contacts in the other half of the cell. The symmetry of the components of each cell is such that the metal interconnection pattern of a cell or a combination of cells for producing a given logic function may be inverted about the horizontal or the vertical plane of symmetry of the cell for producing a logic function relates to said given logic function.