Abstract: Circuits, methods, and apparatus for power MOSFETs having a high cell density for a high current carrying capability while maintaining a low pinched-base resistance. One device employs a number of transistor cells having varying mesa (regions between trench gates) sizes. A heavy body etch is utilized in larger cells to reduce the pinched-base resistance. This etch removes silicon in the mesa region, which is then replaced with lower-impedance aluminum. A number of smaller cells that do not receive this etch are used to increase device current capacity. Avalanche current is directed to the larger, lower pinched base cells by ensuring these cells have a lower BVDSS breakdown voltage. The large cell BVDSS can be varied by adjusting the critical dimension or width of the trench gates on either side of the wider mesas, or by adjusting the depth of the heavy body etch.