Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.

Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

Abstract: In one embodiment, an MOS transistor is formed with trench gates. The gate structure of the trench gates generally has a first insulator that has a first thickness in one region of the gate and a second thickness in a second region of the gate.

Abstract: In one embodiment, a trench semiconductor device is formed to have an oxide of a first thickness along the sidewalls of the trench, and to have a greater thickness along at least a portion of a bottom of the trench.

Abstract: In one embodiment, a transistor is formed to use two conductors to make electrical connection to one of the active regions of the transistor.

Abstract: In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.

Abstract: In one embodiment, a pair of sidewall passivated trench contacts is formed in a substrate to provide electrical contact to a sub-surface feature. A doped region is diffused between the pair of sidewall passivated trenches to provide low resistance contacts.

Abstract: A method of forming a semiconductor device includes forming isolation trenches that are used to isolate some of the electrical elements such as transistors, diodes, capacitors, or resistors on a semiconductor die from other elements on the semiconductor die.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.

Abstract: In one embodiment, a charge compensation region is formed in a body of semiconductor material. A conductive layer is coupled to the charge compensation layer. In a further embodiment, the charge compensation region comprises a trench filled with opposite conductivity type semiconductor layers.

Abstract: In one embodiment, an edge termination structure is formed in a semiconductor layer of a first conductivity type. The termination structure includes an isolation trench and a conductive layer in contact with the semiconductor layer. The semiconductor layer is formed over a semiconductor substrate of a second conductivity type. In a further embodiment, the isolation trench includes a plurality of shapes that comprise portions of the semiconductor layer.

Abstract: In one embodiment, a matrix of free-standing semiconductor shapes are oxidized to form a low capacitance isolation tub. The adjacent rows of shapes in the matrix are offset with respect to each to minimize air gap and void formation during tub formation. In a further embodiment, the spacing between adjacent rows is less than the spacing between shapes within a row.

Abstract: A method of making a semiconductor device (10) includes filling a plurality of trenches (30, 32-34) in a substrate (11) with a first fill material (40, 42-44) and lined with a first liner material (36-39) to form an isolation structure (50) in a first trench (30). The first fill material and the first liner material are removed from a second trench (33) which is then lined with a second liner material (46) and filled with a second fill material (69) to produce a capacitance to the substrate. The first fill material and the first liner material are removed from a third trench (34), which is filled with the second fill material to form an electrical contact to the substrate. The first fill material is removed from a fourth trench (34) and dielectric material (78) is deposited on the substrate to produce a void (83) in the fourth trench.

Abstract: A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Abstract: A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Abstract: A method for making a self-aligned oxide gate cap is provided. The method requires only one photoresist step to make a self-aligned oxide cap that can serve as an implant block and provide self-aligned contacts. A substrate with a gate line is provided. A first oxide layer (36) is then isotropically deposited over the gate line. A portion of the first oxide layer (36) is then etched anisotropically. A second oxide layer (40) is then isotropically deposited over the gate line and the remaining first oxide layer (36). A spacer mask (43) is then formed over the gate line. If preferred, the spacer mask (43) could be extended beyond the spacer region to further separate the drain region from the gate line with dielectric creating a lightly doped drain region. The exposed oxide layer is etched anisotropically, resulting in a dual-step spacer (44) that can act as an implant mask for the source and drain regions and as a self aligned ohmic contact area.

Abstract: A method of manufacturing a semiconductor device gate is provided that reduces gate length variability while maintaining self-alignment and eliminating etch damage and substrate contamination. A gate opening (18) is formed in an oxide layer (16) using a anisotropic etch. The anisotropic etch creates a reverse gate metal image that has low gate length variability. Dual metal gate (26) is then deposited. The excess gate metal is then removed and the top surface (31) of the gate (30) planarized using a chemical mechanical polish. The remaining oxide (16) is then removed, leaving a precise gate (30). The use of a nitride barrier (12) and of an etchstop layer (14) of aluminum nitride under the oxide layer (16) is also shown.

Abstract: The present invention provides a method for plasma dicing a substrate, the method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing a work piece onto the work piece support, said work piece having a support film, a frame and the substrate; loading the work piece onto the work piece support; applying a tensional force to the support film; clamping the work piece to the work piece support; generating a plasma using the plasma source; and etching the work piece using the generated plasma.