Abstract: Embodiments of the invention are directed to providing a method for selecting a link for transmitting a data packet, from links of a Multi-Link Point-to-Point Protocol (MLPPP) bundle, by compiling a list of links having a minimum queue depth and selecting the link in a round robin manner from the list. Some embodiments of the invention further provide for a flag to indicate if the selected link has been assigned to a transmitter so that an appropriate link will be selected even if link queue depth status is not current.

Abstract: A network statistics processing device comprises a port processing unit for determining an update from a forward statistic metric carried by an input PDU, an arbitration unit for placing the updates into a scheduled stream of updates, and a memory unit for storing statistic totals relating to the network operating parameters. The port processing unit also processes the statistic results retrieved from the memory into reverse statistic metrics that are inserted into an output PDU. A statistics monitoring and processing unit enables performance of high level statistical processing on selected updates and on the results. A method of generating and maintaining statistic totals on a plurality of network operating parameters is also described.

Abstract: Switched integrated circuit connection architectures and techniques are disclosed. An integrated circuit includes connection segments and switching elements operatively coupled to the connection segments. Any of multiple switchable connections to a functional module of the integrated circuit can be established, as needed, by the switching elements through the connection segments. Protocol termination points associated with functional modules of the integrated circuit may be addressable in an address space that is used on an external connection outside the integrated circuit. An external protocol used on such an external connection may also be supported internally in the integrated circuit by the protocol termination points.

Abstract: A single chip architecture with multiple programmable processors is described. Each processor has a small and fast acting kernel-based operating system which has primitives for performing only fundamental functions of multi-processing. Many distributed threads may be executed simultaneously on many processors while allowing the device to be programmed as a single monolithic system.

Abstract: Methods and systems of managing processing operations are disclosed. Processing operations are not restricted to being executed by any particular processor of a multi-processor system. Information associated with a processing operation may be transferred to one processor for use by the processor in executing the processing operation. The processor may or may not actually execute the processing operation. Subsequently, information for the processing operation may be transferred to the same processor or a different processor which has capacity to accept the processing operation for execution. The disclosed techniques are not restricted only to multi-processor systems, and may be useful to transfer information between an external memory and processor registers in a single processor system, for example.

Abstract: Systems and methods of controlling transfer of information associated with processing operations, illustratively threads, are disclosed. Instead of transferring information from all storage locations in which information associated with a processing operation is stored for use by a processor in executing the processing operation, a determination is made regarding to or from which, if any, of the storage locations information is to be transferred. Information is then transferred to or from any determined storage locations.

Abstract: A network statistics processing device comprises a port processing unit for determining an update from a forward statistic metric carried by an input PDU, an arbitration unit for placing the updates into a scheduled stream of updates, and a memory unit for storing statistic totals relating to the network operating parameters. The port processing unit also processes the statistic results retrieved from the memory into reverse statistic metrics that are inserted into an output PDU. A statistics monitoring and processing unit enables performance of high level statistical processing on selected updates and on the results. A method of generating and maintaining statistic totals on a plurality of network operating parameters is also described.

Abstract: A method and apparatus for statistical compilation is presented. The statistical compilation circuit includes a multi-bank memory that stores a plurality of statistics, where a statistic component portion for each statistic is stored in each of the plurality of banks in the multi-bank memory. An arbitration block is operably coupled to receive at least one statistical update stream. Each statistical update stream includes a plurality of statistical updates, where each statistical update includes a statistic identifier and an update operand. The arbitration block schedules received statistical updates to produce a scheduled update stream. A control block operably coupled to the arbitration block and the multi-bank memory executes the updates included in the scheduled update stream. The control block retrieves the current value of one of the statistic component portions from one of the memory banks and combines the current value with the update operand of a corresponding statistical update.