Abstract: Apparatus and associated methods relate to packet header field extraction as defined by a high level language and implemented in a minimum number of hardware streaming parsing stages to speculatively extract header fields from among multiple possible header sequences. In an illustrative example, the number of stages may be determined from the longest possible header sequence in any received packet. For each possible header sequence, one or more headers may be assigned to each stage, for example, based on a parse graph. Each pipelined stage may resolve a correct header sequence, for example, by sequentially extracting length and transition information from an adjacent prior stage to determine offset of the next header. By speculatively extracting selected fields from every possible position in each pipeline stage, a correct value may be selected using sequential hardware streaming pipelines to substantially reduce parsing latency.

Abstract: Mining proxy acceleration may include receiving, within a mining proxy, packetized data from a mining pool server and determining, using the mining proxy, whether the packetized data qualifies for broadcast processing. In response to determining that the packetized data qualifies for broadcast processing, the packetized data can be modified using the mining proxy to generate broadcast data. The broadcast data can be broadcast, using the mining proxy, to a plurality of miners subscribed to the mining proxy.

Abstract: A match-action circuit includes one or more conditional logic circuits, each having an input coupled to input header or metadata of a network packet, and each configured to generate an enable signal as a function of one or more signals of the header or metadata. Each match circuit of one or more match circuits is configured with response values associated with key values. Each match circuit is configured to conditionally lookup response value(s) associated with an input key value from the header or metadata in response to the enable signal from a conditional logic circuit. One or more action circuits are configured to conditionally modify, in response to states of the response value(s) output from the match circuit(s), data of the header or the metadata.

Abstract: A device includes a programmable passive measurement hardware engine, a programmable active measurement hardware engine, and a configuration engine. The programmable passive measurement hardware engine is configured to collect statistical data, from data transmission at a network line rate, used for network measurement. The programmable active measurement hardware engine is configured to generate probe packets and wherein the programmable active measurement hardware engine is further configured to collect responses to the generated probe packets, wherein the collected responses are used for the network measurement. The configuration engine is configured to receive data settings and wherein the configuration engine is further configured to program the programmable passive measurement hardware engine and the programmable active measurement hardware engine with the received data settings.

Abstract: Apparatus and associated methods relating to data packet deparsing include an editing circuit configured to perform one or more predetermined editing operations on headers of an incoming data packet step by step without extracting all headers from the incoming data packet. In an illustrative example, an editor circuit may include an updating circuit configured to receive the data packet and update a header in the data packet. The editor circuit may also include a removal circuit configured to remove a header from the data packet. The editor circuit may also include an insertion circuit configured to insert one or more consecutive headers to the data packet. A state machine may be configured to enable or disable the updating circuit, the removal circuit, and/or the insertion circuit based on the predetermined editing operations. By using the editing circuit, packet deparsing may be performed with less hardware resources and low latency.

Abstract: Methods and apparatus for using dynamic programming to determine the most efficient mapping of a pipeline of virtual flow tables (VFTs) onto a pipeline of physical flow tables (PFTs) in the data plane of a software-defined networking (SDN) device are described. One example method of determining a configuration for an SDN device generally includes receiving a representation of a series of one or more VFTs, each of the VFTs having one or more properties; receiving a representation of a series of one or more PFTs for hardware of the SDN device, each of the PFTs having one or more capabilities; generating, using dynamic programming based on the properties of the VFTs and the capabilities of the PFTs, a mapping of the series of VFTs onto the series of PFTs; and outputting the generated mapping for implementation on the hardware of the SDN device.

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract: In one approach for processing a data packet, in at least one stage of a plurality of stages of a pipeline circuit, a respective packet field value is extracted from the data packet. In each stage of the plurality of stages, a respective tuple field value is inserted into a respective tuple register of the stage at a respective offset. The respective tuple field value in the at least one stage is based on the respective packet field value. In each stage of the plurality of stages except a last one of the stages, the contents of the respective tuple register of the stage are provided as input to a next one of the stages.

Abstract: In an FSM circuit, look-ahead-cascade modules are coupled to receive possible states and corresponding subsets of data inputs. Merge modules are coupled to a second-to-the-lowest to highest order of the look-ahead-cascade modules. The second-to-the-lowest to highest order of disambiguation modules are coupled to at least a portion of the merge modules. The lowest order of the disambiguation modules is coupled to the lowest order of the look-ahead-cascade modules. The lowest-to-highest order of the disambiguation modules are coupled to receive respective sets of interim states of rN states each to select respective sets of next states of r states each. A state register is coupled to receive a portion of the highest order of the sets of next states to provide a select signal. Each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states of the r states each.

Abstract: An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.

Abstract: A packet processing circuit includes a plurality of header extraction circuits, and a scheduling circuit coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus having a plurality of data lanes. In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the request, and assigns a respective one of the plurality of header extraction circuits to extract respective header data from the first subset of the plurality of data lanes.

Abstract: A network packet processor includes a plurality of processing pipelines and a scheduling circuit. Each processing pipeline is configured and arranged to process packets having sizes less than or equal to an associated processing size of the processing pipeline. The respective processing size of one of the processing pipelines is different from the processing size of at least one other of the processing pipelines. The scheduling circuit is coupled to the plurality of processing pipelines and is configured and arranged to determine respective packet sizes of packets input from a bus. The scheduling circuit assigns each packet of the one or more packets for processing by one of the processing pipelines as a function of the respective packet size of the packet and the processing size associated with the one of the processing pipelines.

Abstract: Approaches for dynamically reconfiguring a programmable integrated circuit (IC) are disclosed. In response to user input to a reconfiguration controller while a circuit is operating in programmable resources of the programmable IC, a replacement module and a module to be replaced in the circuit are selected. A process determines whether or not interfaces of the replacement module are compatible with interfaces of the circuit to the module to be replaced. In response to the interfaces of the replacement module and the interfaces of the circuit to the module to be replaced being compatible, the programmable IC is partially reconfigured with a realization of the replacement module in place of a realization of the module to be replaced.

Abstract: A packet processor includes a memory and a programmable compute pipeline. The memory stores microcode that specifies respective sets for the packet types, and the respective set for each type specifies packet fields. The programmable compute pipeline includes a sequence of stages beginning with an initial stage. The initial stage includes an operand selector that extracts a data vector from each packet. The operand selector is programmable to extract the data vector that includes each field specified in the respective set for the type of each packet. Each stage except the initial stage inputs a first version of the data vector and each stage outputs a second version of the data vector. Each stage except the initial stage generates the second version of the data vector that replaces a part of the first version of the data vector with a result that the stage computes from the part.

Abstract: An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.

Abstract: A packet processing circuit includes a plurality of header extraction circuits, and a scheduling circuit coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus having a plurality of data lanes. In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the request, and assigns a respective one of the plurality of header extraction circuits to extract respective header data from the first subset of the plurality of data lanes.

Abstract: A packet processor includes a memory and a programmable compute pipeline. The memory stores microcode that specifies respective sets for the packet types, and the respective set for each type specifies elementary operations for each stage except an initial stage of the programmable compute pipeline. The programmable compute pipeline includes a sequence of stages beginning with the initial stage. The initial stage includes an operation selector that selects the respective set for the type of each packet. Each stage except the initial stage includes elementary components that are programmable to concurrently perform each of multiple combinations of elementary operations. The elementary components concurrently perform a selected one of the combinations for each packet. The selected combination includes the elementary operations specified for the stage in the respective set that the operation selector selects for the packet's type.

Abstract: A method or system for generating a packet processor inputs a first specification describing the packet processor, generates a parsing tree and generates a second specification describing a programmable compute pipeline. The parsing tree is generated from the actions of the first specification. The parsing tree has multiple levels and each level specifies one or more concurrent sets of elementary operations. The parsing tree also specifies for each level a respective bound on the elementary operations in the concurrent sets of the level. The programmable compute pipeline includes multiple stages for implementing the actions. Each stage corresponds to one of the levels of the parsing tree and includes one or more elementary components, with a number of the elementary components equaling or exceeding the respective bound for the level. The elementary components in the stage are programmable to concurrently perform combinations that include each concurrent set for the level.

Abstract: A circuit manages input and output formats of the packets of a communication protocol. The circuit includes representation blocks and distribution and gather blocks coupled to the representation blocks. Each representation block is associated with a respective descriptor of the input and output formats. Each representation block processes a value of the respective descriptor. One or more of the representation blocks is adapted to modify the value of the respective descriptor. For each packet input in the input format, the distribution block distributes the value of each descriptor for the packet to the representation block associated with the descriptor. For each packet output in the output format, the gather block gathers the value of each descriptor for the packet from the representation block associated with the descriptor. The input format is changed to the output format in response to representation blocks modifying the value of the respective descriptor.

Abstract: A computer-implemented method of developing a packet processing application can include receiving a user input specifying a first function and a second function and automatically generating a high level programming language description of the packet processing application including a packet data storage unit (605, 610, 615). Packet units can be stored within the packet data storage unit at locations determined according to the first function and the second function. The high level programming language description also can be stored (630).