Abstract: Disclosed is an apparatus which shows the use of an inwardly disposed set of C4 type I/O connections to an integrated circuit chip over and above the typical peripherally disposed set of I/O connections which use wire type connections between the chip and other circuitry of a substrate upon which the chip is mounted. The inwardly disposed set of connections may be used to provide a direct connection to an optional ancillary chip having a corresponding set of I/O connection points. Such a construction not only increases the number of possible I/O connections, but additionally increases the bandwidth of communications between the directly connected chips.

Abstract: A transitioning of power dissipation in a processing device (11) is coordinated with the operation of a cooling system (16, 17, 18) for the processing device. A power transitioning arrangement (15) transitions power dissipation in the processing device (11) between a high power level and a relatively lower low power level. In conjunction with a transitioning of the processing device power level, the cooling system (16, 17, 18) is placed in either a high or low thermal impedance state to reduce the rate at which the temperature of the data processing device (11) and related elements change in response to the change in power dissipated by the processing device. Transitioning the power dissipation in the processing device (11) may be accomplished by gradually varying the clock rate for the device, by changing the clock rate to various processing elements in the device at different times, and/or by changing the instruction issue rate in the device.

Abstract: The present invention discloses a microprocessor bus structure that enables a processor chip to be designed with optional unidirectional or bi-directional I/O buses. The processor is designed with separate input and output bus internal to the chip. A gating network is coupled to these processor uni-directional busses that allows the chip to have an alternate externally wired bus structure. For the lowest cost and lowest performance only one set of bidirectional bus lines are wired external to the chip. These lines have a parallel driver and receiver with appropriate gating to allow the bus to be either in the send or receive mode. The signals from the processor uni-directional input and output buses are wired via appropriate gating to create a single bi-directional bus.

Abstract: A multi-processor system and methodology optimize overhead costs associated with manufacturing large integrated circuit devices having multiple data processors and processing elements thereon by effectively disabling processing elements that are not functional. Disabling the processing elements is performed through segmented power distribution on an integrated circuit first-level package or by providing inhibit signals in pre-selected logic states based on the functionality of the multi-processing system. The functionality of the multiprocessing system is determined during an initial testing procedure, including wafer-level testing.

Abstract: A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Abstract: A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Abstract: A memory cube comprising a plurality of memory chips, each having a plurality of data storage devices, is provided with an auxiliary chip having inactive line termination circuits and the auxiliary chip or chips are formed as part of the memory cube structure and disposed among the memory chips on an interleave basis. The auxiliary circuit chips are provided with external terminals connected to memory input leads, control leads and data write leads, in close proximity to the termination point of the leads. A decoupling capacitor, integrated in the auxiliary circuit chip, is connected to the power bus in the memory cube structure and eliminates extraneous noise problems occurring with discrete capacitors external to the cube. A heating resistor is provided on the auxiliary circuit chip to maintain the cube structure at a near constant temperature. Temperature sensing diodes are incorporated in the auxiliary chip to provide an accurate mechanism for sensing the temperature internal to the cube.

Abstract: A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Abstract: A thin-film arrangement for a non-planar structure is described. The structure includes a substrate and a plurality of thin-film layers stacked on top of each other above the substrate. The layers contain conductive patterns and vias that provide connections between the conductive pattern in one of the layers to the conductive pattern in another layer. Vias that provide a connection between the conductive pattern of one layer to the conductive pattern in another remotely located layer are offset and in contact with respect to each other and are positioned in a non-linear arrangement, preferably in the form of a helix or a multiple helix.

Abstract: A waveguide structure is directly extruded onto a surface from a nozzle placed a predetermined distance above the surface and which is moved relative to the surface, preferably by means of a translation table. The predetermined distance is preferably maintained constant and the speed of relative motion regulated to achieve a uniform degree of molecular orientation within the extruded material, thus maintaining a sufficiently uniform refractive index along the axis of the waveguide. Partitions within the nozzle allow the formation of a layered waveguide or the simultaneous formation of concentric cladding or protective layers. The waveguides are advantageously formed as a curtain which is later patterned, by direct writing on the surface or between chips mounted on an electronic module.

Abstract: Disclosed is an optical signal distribution system. The system comprises an electronic substrate, at least one optical component and at least one optical waveguide on but distinct from the electronic substrate for carrying an optical signal to or from the optical component.

Abstract: A Level Sensitive Scan Design (LSSD) Shift Register Latch pair implemented in current switch logic is disclosed. The arrangement is characterized by the logic used to control the L1 and L2 latches being implemented in Differential Cascode Current Switch logic and the L1/L2 latches being coupled to only one current source. A "merged" L1/L2 latch arrangement employing only one current source is provided for an LSSD testing environment.