Abstract: An example method for generating bus addresses for slave devices on a two wire interface bus includes providing a base address to each of N slave devices connected to the two wire interface bus and providing a sequence of N?1 clock pulses to each of the N slave devices to provide unique bus addresses. Circuitry within each of the example slave devices is operative to receive a base address followed by a plurality of clock pulses from the host device and to increment the base address by a digital integer. Circuitry within each of the example slave devices is further operative to terminate incrementing of the base address when an inhibit logic signal is detected at the slave program input and to save an address resulting from incrementing the base address as a bus address subsequent to terminating the incrementing of the base address.

Abstract: The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: A switching matrix has a plurality of inputs and outputs which may be connected to each other. Pairs of inputs and outputs are examined sequentially to determine whether a connection can be made across the matrix. If the evaluated input and output are busy a connection cannot be made, and the input remains idle. When a connection can be made a connection is scheduled, taking into account the time for which that connection has been available. Inputs and outputs have controllers which continuously monitor, e.g. by using counters, the time for which connections have been available. Idle time at inputs is reduced, thereby increasing switching capacity. The switching matrix may be one which handles ATM traffic.