Abstract: A bus interface device includes a parallel input configured to be coupled to a bus (20), such as a primary PCI bus. The device also includes a parallel data output (TXD) and at least two control output nodes (TX_ER and TX_EN). Data control circuitry coupled to the control output nodes utilizes a coding scheme (e.g., an 8B/10B scheme) to generate one of a set of control codes (e.g., Idle, Extend, Normal Data and Error) to be provided to the control output nodes. The device also includes reset control circuitry that generates a specified sequence of control codes (e.g., a sequence of Idle's and Extend's) on the control outputs. This sequence can be used to communicate information such as a signal (e.g., reset signal) and/or a mode (e.g., a CRC mode).

Abstract: A first embodiment of the present invention includes a decoder 320 and a detection circuit 330. The decoder 320 receives data at a packet rate. Each packet includes more than one word so that the packet rate is less than a word rate. The detector circuit 330 monitors a data valid signal from the decoder 320 and asserts an output signal (send idle) upon determination that the data valid signal changes values at a rate higher than the packet rate.