Abstract: Female fiber optic connectors having a weatherproofing collar disposed rearward of a connection port opening that receives a fiber optic plug along with cable assemblies comprising the female fiber optic connector and with methods of making the same. The female fiber optic connectors comprise an actuator such as a rocker latch arm or the like disposed under the weatherproofing collar used for releasing or securing an external fiber optic plug that may be received in the connection port. The weatherproofing collar protects the actuator such as the rocker arm latch and surrounding area from dirt, debris, moisture and the like from ingress into the connector. One or more end caps may be used with the weatherproofing collar. The weatherproofing collar allows for a ruggedized fiber optic connector having a quick connect and release mechanism for the external fiber optic plug connector mated to the female fiber optic connector.

Abstract: A protective device in a semiconductor may comprise a substrate of a first conductivity type, an epitaxial layer formed on top of the substrate, a body area formed within the epitaxial layer of a second conductivity type extending from a top surface into the epitaxial layer, a first area of the first conductivity type extending from the top surface into the body area, an isolation area surrounding the first area, a ring area of the first conductivity type surrounding the isolation area, and a coupling structure for connecting the ring area with the substrate.

Abstract: An LDMOS transistor comprises source, channel and extended drain regions. The extended drain region comprises a plurality of islands that have a conductivity type that is opposite to the extended drain region. The islands have a depth less than a depth of the extended drain region.

Abstract: A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure comprising a via for coupling the drain runner with the drain region, and a second coupling structure comprising a via for coupling the source runner with the source region.

Abstract: An LDMOS transistor comprises source, channel and extended drain regions. The extended drain region comprises a plurality of islands that have a conductivity type that is opposite to the extended drain region. The islands have a depth less than a depth of the extended drain region.

Abstract: An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial layer of a second conductivity type, a channel located between the drain and source regions, and a gate arranged above the channel within an insulating layer, wherein the lightly doped drain region comprises an implant region of the first conductivity type extending from the surface of the epitaxial layer into the epitaxial layer covering an end portion of the lightly doped drain region next to the gate.

Abstract: A protective device in a semiconductor may comprise a substrate of a first conductivity type, an epitaxial layer formed on top of the substrate, a body area formed within the epitaxial layer of a second conductivity type extending from a top surface into the epitaxial layer, a first area of the first conductivity type extending from the top surface into the body area, an isolation area surrounding the first area, a ring area of the first conductivity type surrounding the isolation area, and a coupling structure for connecting the ring area with the substrate.

Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.

Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.

Abstract: A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure comprising a via for coupling the drain runner with the drain region, and a second coupling structure comprising a via for coupling the source runner with the source region.

Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.

Abstract: A semiconductor device has a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor with a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure with a via for coupling the drain runner with the drain region, and a second coupling structure with a via for coupling the source runner with the source region.

Abstract: An LDMOS semiconductor transistor structure comprises a substrate having an epitaxial layer of a first conductivity type, a source region extending from a surface of the epitaxial layer of a second conductivity type, a lightly doped drain region within the epitaxial layer of a second conductivity type, a channel located between the drain and source regions, and a gate arranged above the channel within an insulating layer, wherein the lightly doped drain region comprises an implant region of the first conductivity type extending from the surface of the epitaxial layer into the epitaxial layer covering an end portion of the lightly doped drain region next to the gate.

Abstract: A semiconductor device comprises an active region of a first conductivity type including a transistor structure, and a ring shaped region of the first conductivity type extending from a surface of the active region into the active region and substantially surrounding the transistor structure.

Abstract: A semiconductor transistor structure includes a substrate having an epitaxial layer, a source region extending from the surface of the epitaxial layer, a drain region within the epitaxial layer, a channel located between the drain and source regions, and a gate arranged above the channel. The drain region includes a first region for establishing a contact with an electrode, a second region being less doped than the first region being buried within the epitaxial layer and extending from the first region horizontally in direction towards the gate, a third region less doped than the second region and extending vertically from the surface of the epitaxial layer and horizontally from the second region until under the gate, a top layer extending from the surface of the epitaxial layer to the second region, and a bottom layer extending from the second region into the epitaxial layer.

Abstract: A semiconductor device comprises a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor comprising a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure comprising a via for coupling the drain runner with the drain region, and a second coupling structure comprising a via for coupling the source runner with the source region.

Abstract: A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.

Abstract: A semiconductor transistor structure comprises a substrate having an epitaxial layer, a source region extending from the surface of the epitaxial layer, a drain region within the epitaxial layer, a channel located between the drain and source regions, and a gate arranged above the channel. The drain region comprises a first region for establishing a contact with an electrode, a second region being less doped than the first region being buried within the epitaxial layer and extending from the first region horizontally in direction towards the gate, a third region less doped than the second region and extending vertically from the surface of the epitaxial layer and horizontally from the second region until under the gate, a top layer extending from the surface of the epitaxial layer to the second region, and a bottom layer extending from the second region into the epitaxial layer.

Abstract: A semiconductor device comprises an active region of a first conducting type including a transistor structure, and a ring shaped region of the first conducting type extending from a surface of the active region into the active region and substantially surrounding the transistor structure.