Abstract: A method is described. The method includes repeatedly reading accelerator telemetry data from register and/or memory space allocated for the keeping of the accelerator telemetry data and writing the accelerator telemetry data into a physical file structure within memory and/or mass storage. The method also includes repeatedly reading the accelerator telemetry data from the physical file structure and storing the accelerator telemetry data into virtual files that are visible to application software programs that invoke the accelerator. The accelerator telemetry data describes an input/output memory management unit’s performance regarding its translation of virtual addresses to physical addresses for the accelerator.

Abstract: An apparatus is described. The apparatus includes a memory management unit. The memory management unit is to receive a memory access request from an accelerator, wherein the memory access request includes a virtual address of a payload provided by an application that invokes the accelerator to perform a function on the payload, wherein. The memory access request also includes an identifier of the application's CPU process. The memory management unit is to translate the virtual address to a physical address to fetch the payload from a location allocated to the application within a memory.

Abstract: An accelerator apparatus can include an interface to receive service requests from at least one processing core. The accelerator apparatus can include coprocessor circuitry coupled to the interface and comprised of multiple slices. The coprocessor circuitry can detect a performance type for the at least one processing core. The coprocessor circuitry can operate the plurality of coprocessor slices in at least one of a plurality of power modes based on the performance type detected for the at least one processing core. Some operations can be alternatively performed by an operating system on any processor coupled to the network.

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

Abstract: In one embodiment, a method comprises determining, at a plurality of instances in time, a value of at least one stress characteristic of a hardware resource; determining an accumulated stress value of the hardware resource, the accumulated stress value comprising the sum of a plurality of incremental stress values, an incremental stress value determined based on the value of the at least one stress characteristic at a particular instance in time; and generating a first stress indicator in response to a determination that the accumulated stress value of the hardware resource is greater than a first threshold stress value associated with the hardware resource.

Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that include a reliability physics module stored in non-volatile memory and compute logic to calculate at least one of an estimated amount of lifetime consumed or an estimated amount of lifetime remaining after a period of operation of an integrated circuit. In embodiments, the calculation may be based at least in part on the reliability physics model and data of at least one physical condition of the integrated circuit sensed during or at the end of the period of operation. Other embodiments may be described and/or claimed.

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

Abstract: Hardware processors and methods to perform self-monitoring diagnostics to predict and detect failure are described. In one embodiment, a hardware processor includes a plurality of cores, and a diagnostic hardware unit to isolate a core of the plurality of cores at run-time, perform a stress test on an isolated core, determine a stress factor from a result of the stress test, and store the stress factor in a data storage device.

Abstract: In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.

Abstract: Described are a system and method of forwarding ATM cells among component boards in a computing platform. ATM cells received at an ingress media port of component board may be forwarded to a destination component board in a payload portion of an Ethernet data frame comprising at least one field identifying an egress port of a destination component board for transmitting the forwarded ATM cells.