Patents by Inventor Gordon P. Lee

Gordon P. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9436479
    Abstract: A method, an apparatus, and a computer program product for booting the apparatus with a low-energy battery are provided. In a first configuration, the apparatus monitors a level of the battery while the battery is charging. The apparatus attempts a boot of the apparatus when the level is greater than or equal to a dynamic boot threshold. The apparatus increases the dynamic boot threshold when the boot is unsuccessful and repeating the monitoring and the attempting based on the increased dynamic boot threshold. In a second configuration, the apparatus detects a connection to an external power source. The apparatus attempts a boot using an FLCB protocol that is based upon power drawn directly from the external power source upon detecting the connection to the external power source. The apparatus attempts the boot as part of an ATC protocol when the boot using the FLCB protocol is unsuccessful.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: September 6, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Gordon P. Lee, Eric B. Zeisel, Jennifer A. Hagstrom, Cheong Kun
  • Patent number: 9119162
    Abstract: A method and apparatus for extending the driving capacity of a power management device are provided. The method involves determining an energy requirement for the operation of a power management device. Next, the method compares the energy requirement for the operation of a power management device with a capability of a first power device. If the energy requirement is greater than the energy requirement of the first power device, the energy is switched to a second power device of higher capacity. The apparatus includes: a first power device; a second power device connected in parallel to the first power device; a first inductor connected to the first power device and a capacitor connected to the first inductor; and a second inductor connected to a second power device and a capacitor connected to the second inductor.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: August 25, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Adrian M Stenzel, Todd R Sutton, Narendra Singh Mehta, Siegfried W Breitmeier, Gordon P Lee
  • Patent number: 9047415
    Abstract: A method for media access control, the method includes generating at least one media access grant in response to at least one media access request. The method further includes monitoring a data line, while maintaining at least a clock line in a low power mode, to detect at least one media access request generated by at least one component connected to the data line and to the clock line; and forcing the at least clock line to exit the low power mode and starting a contention prevention period, when the media access controller or at least one component requests to access the data line. Also disclosed is a device for implementing the method of media access control.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: June 2, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Christopher Chun, Gordon P. Lee, Cor Voorwinden
  • Publication number: 20140235299
    Abstract: A method and apparatus for extending the driving capacity of a power management device are provided. The method involves determining an energy requirement for the operation of a power management device. Next, the method compares the energy requirement for the operation of a power management device with a capability of a first power device. If the energy requirement is greater than the energy requirement of the first power device, the energy is switched to a second power device of higher capacity. The apparatus includes: a first power device; a second power device connected in parallel to the first power device; a first inductor connected to the first power device and a capacitor connected to the first inductor; and a second inductor connected to a second power device and a capacitor connected to the second inductor.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 21, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Adrian M. Stenzel, Todd R. Sutton, Narendra Singh Mehta, Siegfried W. Breitmeier, Gordon P. Lee
  • Publication number: 20120185684
    Abstract: A method, an apparatus, and a computer program product for booting the apparatus with a low-energy battery are provided. In a first configuration, the apparatus monitors a level of the battery while the battery is charging. The apparatus attempts a boot of the apparatus when the level is greater than or equal to a dynamic boot threshold. The apparatus increases the dynamic boot threshold when the boot is unsuccessful and repeating the monitoring and the attempting based on the increased dynamic boot threshold. In a second configuration, the apparatus detects a connection to an external power source. The apparatus attempts a boot using an FLCB protocol that is based upon power drawn directly from the external power source upon detecting the connection to the external power source. The apparatus attempts the boot as part of an ATC protocol when the boot using the FLCB protocol is unsuccessful.
    Type: Application
    Filed: November 8, 2011
    Publication date: July 19, 2012
    Applicant: QUALCOMM Incorporated
    Inventors: Gordon P. Lee, Eric B. Zeisel, Jennifer A. Hagsfrom, Cheong Kun
  • Patent number: 8223910
    Abstract: A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: July 17, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, Christopher K. Y. Chun, Gordon P. Lee, Cor Voorwinden
  • Patent number: 7834417
    Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) includes a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) includes one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) is defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: November 16, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Robert W. Baird, Gordon P. Lee, Jiang-Kai Zuo
  • Publication number: 20090224325
    Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) includes a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) includes one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) is defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
    Type: Application
    Filed: March 27, 2009
    Publication date: September 10, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Won Gi Min, Robert W. Baird, Gordon P. Lee, Jiang-Kai Zuo
  • Publication number: 20090175393
    Abstract: A method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; characterized by defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle. A device having frame synchronization capabilities, the device includes a clock signal provider and at least one component connected to a data line. The clock signal provider is adapted to provide a high frequency clock signal over a clock line during a transmission of information over the data line.
    Type: Application
    Filed: June 10, 2005
    Publication date: July 9, 2009
    Applicant: SANIT-GOBAIN GLASS FRANCE
    Inventors: Michael Priel, Christopher Chun, Gordon P. Lee, Cor Voorwinden
  • Patent number: 7553704
    Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) including the fabrication of one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: June 30, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Robert W. Baird, Jiang-Kai Zuo, Gordon P. Lee
  • Publication number: 20080313479
    Abstract: A method for media access control, the method includes generating at least one media access grant in response to at least one media access request. The method is characterized by monitoring a data line, while maintaining at least a clock line in a low power mode, to detect at least one media access request generated by at least one component connected to the data line and to the clock line; and forcing the at least clock line to exit the low power mode and starting a contention prevention period, when the media access controller or at least one component requests to access the data line. A device including multiple components that are connected to a data line, and adapted to transmit information over the data line at a transmission rate responsive to a first clock rate.
    Type: Application
    Filed: June 10, 2005
    Publication date: December 18, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Priel, Christopher Chun, Gordon P. Lee, Cor Voorwinden
  • Patent number: 7256471
    Abstract: An antifuse element (102) having end corners (120, 122) of a gate electrode (104) positioned directly above an active area (106) or bottom electrode. The minimum programming voltage between the gate electrode (104) and the active area (106) creates a current path through an insulating layer (110) positioned therebetween. The high electric field created at the end corners (120, 122) of the gate electrode (104) results in a breakdown and rupture of the insulating layer (110) at points directly beneath the end corners (120, 122). This localization of the insulating layer (110) at the corners (120,122) provides for lower post program resistance and variation, and faster programming at a lower programming power. The antifuse elements (102) when integrated into an array (300, 320, 400, 550) provide for increased packing density. The array is fabricated to include multiple active areas (304) for individual antifuse element (302) programming or a common active area (324,405,426,506) for multi-element programming.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: August 14, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Won Gi Min, Robert W. Baird, Jiang-Kai Zuo, Gordon P. Lee
  • Patent number: 7190279
    Abstract: A light modulation system as described herein can be incorporated into a personal or portable electronic apparatus such as a cellular telephone, a digital music player, or the like. The light modulation system controls the activation of light elements, such as light emitting diodes, of the host electronic apparatus in response to one or more analog audio signals available at the host electronic apparatus. The analog audio signals may be obtained from any suitable analog audio path or source in the host electronic apparatus. The light modulation system is compact, inexpensive to implement, and need not rely on digital signal processors for operation.
    Type: Grant
    Filed: February 22, 2005
    Date of Patent: March 13, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Youssef H. Atris, Brandt Braswell, Brian E. Chang, Gordon P. Lee
  • Patent number: 7085943
    Abstract: Supply voltages within a data processing system may be controlled by a voltage control module which can provide digital signals to a power management unit to cause changes in supply voltages without software intervention. For example, in one embodiment, a voltage control signal and a standby signal may be provided to control the supply voltages output by a voltage regulator within the power management unit. In one embodiment having multiple processors, a voltage control signal and a standby signal corresponding to each processor may be provided to the power management unit which has a voltage regulator supplying an independently controlled supply voltage to each processor. Alternatively, a voltage regulator, a voltage control signal, and a standby signal may be shared by multiple processors, where the voltage control module may ensure that the supply voltage is changed only when the change is appropriate for all processors sharing the same voltage regulator.
    Type: Grant
    Filed: September 26, 2003
    Date of Patent: August 1, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christopher K. Y. Chun, Wayne W. Ballantyne, Gordon P. Lee, Scott A. Tassi, Darren V. Weninger
  • Patent number: 5101669
    Abstract: A multibeam structure measures displacement of one or more response elements to detect multiple components of applied force. The flexible beams are each coupled to a response element which may be displaced by a force arising from linear acceleration, angular acceleration, fluid flow, electric/magnetic/gravitational fields, and other sources. The displacement of the response element is detected with a variety of sensing methods including capacitive and piezoresistive sensing.
    Type: Grant
    Filed: May 11, 1990
    Date of Patent: April 7, 1992
    Assignee: University of Hawaii
    Inventors: James W. Holm-Kennedy, Gordon P. Lee
  • Patent number: 5095762
    Abstract: A multibeam structure measures displacement of one or more response elements to detect multiple components of applied force. The flexible beams are each coupled to a response element which may be displaced by a force arising from linear acceleration, angular acceleration, fluid flow, electric/magnetic/gravitational fields, and others sources. The displacement of the response element is detected with a variety of sensing methods including capacitive and piezoresistive sensing.
    Type: Grant
    Filed: May 11, 1990
    Date of Patent: March 17, 1992
    Assignee: University of Hawaii
    Inventors: James W. Holm-Kennedy, Gordon P. Lee, Michael H. Kaneshiro
  • Patent number: 5083466
    Abstract: A multibeam structure measures displacement of one or more response elements to detect multiple components of applied force. The flexible beams are each coupled to a response element which may be displaced by a force arising from linear acceleration, angular acceleration, fluid flow, electric/magnetic/gravitational fields, and others sources. The displacement of the response element is detected with a variety of sensing methods including capacitive and piezoresistive sensing.
    Type: Grant
    Filed: May 11, 1990
    Date of Patent: January 28, 1992
    Assignee: University of Hawaii
    Inventors: James W. Holm-Kennedy, Gordon P. Lee, Michael H. Kaneshiro
  • Patent number: 4951510
    Abstract: A multibeam structure measures displacement of one or more response elements to detect multiple components of applied force. The flexible beams are each coupled to a response element which may be displaced by a force arising from linear acceleration, angular acceleration, fluid flow, electric/magnetic/gravitational fields, and others sources. The displacement of the response element is detected with a variety of sensing methods including capacitive and piezoresistive sensing.
    Type: Grant
    Filed: July 14, 1988
    Date of Patent: August 28, 1990
    Assignee: University of Hawaii
    Inventors: James W. Holm-Kennedy, Gordon P. Lee, Michael H. Kaneshiro