Abstract: A signal synchronization mapper for mapping an input data stream characterized by a first frequency (typically a SONET/SDH stream) into an output data stream characterized by a second frequency. A phase lock control loop containing a “delta-sigma” (&Dgr;-&Sgr;) modulator which functions as a voltage controller oscillator synchronizes the data rate of the output stream to that of the input stream in a manner which simplifies attenuation of jitter energy when the output data stream is desynchronized (demapped). The modulator generates an accurate pulse train by duty-cycle dithered modulation of the input stream, which the mapper interprets as stuff/nullide-stuff commands such that the mapping operation is lossless over time (i.e. the number of bits in equals the number of bits out over time) thus allowing utilization of a FIFO buffer without the need to monitor the buffer's depth or its pointers.