Abstract: A high voltage tolerant CMOS output driver circuit and high voltage tolerant CMOS input receiver circuit, through the use of shield transistors and the redefinition of the substrate of the PFET devices, is provided. The invention may be incorporated for protection in integrated circuits operating with a lower power supply voltage than externally interfaced devices operating with a higher power supply voltage.

Abstract: The output impedance in a CMOS output driver stage is programmed and compensated by complementary current mirrors that are MOS devices in series with each of the conventional pull-up and pull-down devices. The conduction of these additional complementary devices is controlled according to complementary programming signals that are compensated for variations in manufacturing process parameters as well as for changes in temperature. A P-type programming signal may be referenced to +VDD and be produced from an N-type programming signal referenced to GND by the action of a gate voltage mirror that includes symmetrical N-type and P-type FET's in series. The N-type programming signal may be produced in the first instance from the gate voltage of an N-type FET used in a feedback loop that servos an external programming voltage to track an internally generated reference voltage. That gate voltage exhibits variations that reflect differences attributable to both process variations and to temperature.

Abstract: ESD protection for an integrated circuit having a dirty ground is increased by including an SCR or other protection device from dirty ground to each pad whose driver uses dirty ground. The SCR or other protection device (if triggerable) is triggered by a sensing circuit that is referenced to dirty ground. If there is more than one dirty ground then the one that is used is the dirty ground that is associated with the pad to be protected. Pads not using a dirty ground may also be protected with respect to a dirty ground. A p-type substrate library cell for ESD protection of a pad may be developed that includes a first SCR from the pad to ground, a trigger circuit referenced to ground for the first SCR, a second SCR from the pad to a dirty ground, and a trigger circuit referenced that dirty ground for the second SCR. The trigger circuit for the library cell uses the presence or absence of V.sub.DD to provide high or low threshold voltages for triggering the SCR. For n-type substrates where V.sub.DD and DV.sub.

Abstract: A CMOS latch circuit having a second feedback inverter and a switching circuit to switch the second feedback inverter out of the circuit when the latch is being loaded. A first circuit implementation uses a single PFET as the switching circuit, and a second circuit implementation incorporates an NFET transistor, in parallel with the PFET. In a third circuit implementation, the switching circuit switches power to and from the second feedback inverter rather than switching the output signal of the inverter to reduce the input capacitance of the latch.

Abstract: An ESD protection circuit that uses the well-known SCR latchup effect present in CMOS processes to divert the ESD current pulse away from sensitive circuit structures. The circuit uses an inverter trigger device, with a voltage divider on its output, to control the amount of voltage necessary to cause latchup. This feature enables the SCR to absorb a high current pulse on the CMOS pad structures caused by an ESD event, while also preventing the circuit from latching when an ordinary CMOS voltage is applied to the pad while the circuit being protected is unpowered. The circuit insures that the SCR will latch independent of breakdown effects, while also allowing the threshold voltage at which latchup occurs to be adjusted into the circuit by varying the sizes of two FETS used as the voltage divider.