Abstract: Disclosed is a demultiplexer for demultiplexing a multiplexed stream, obtained on time division multiplexing a plurality of elementary streams. A buffer controller, forming this demultiplexer, writes a multiplexed stream, beginning from a location specified by a data write pointer of a ring buffer, configured for storing data of the multiplexed stream, in the manner of an endless loop. On receipt of an ES1 readout request, an ES1 readout control unit takes out, from an ES1 readout pointer storage unit, a readout pointer, as a start point of retrieving an area in the ring buffer where the oldest ES1 is stored. The ES1 readout control unit then retrieves and reads out the ES1, with a location specified by the ES1 readout pointer, as a start point, and sends the ES1, thus read out, to the source of the request. The ES1 readout control unit then updates the ES1 readout pointer and the data leading end pointer.

Abstract: At step S372, permission information about video data that are being reproduced is obtained from permission information that represents whether video data corresponding to encoded video data equal to or larger than an access unit are permitted to be secondarily used. At step S373, it is determined whether the video data that are being reproduced have been permitted to be secondarily used corresponding to the permission information. When it has been determined that the video data that are being reproduced have been permitted to be secondarily used, at step S376, the video data that are being reproduced are captured. At step S381, a process using the captured video data is executed. The present invention can be applied to for example a game device that uses a DVD.

Abstract: Disclosed is a demultiplexer for demultiplexing a multiplexed stream, obtained on time division multiplexing a plurality of elementary streams. A buffer controller, forming this demultiplexer, writes a multiplexed stream, beginning from a location specified by a data write pointer of a ring buffer, configured for storing data of the multiplexed stream, in the manner of an endless loop. On receipt of an ES1 readout request, an ES1 readout control unit takes out, from an ES1 readout pointer storage unit, a readout pointer, as a start point of retrieving an area in the ring buffer where the oldest ES1 is stored. The ES1 readout control unit then retrieves and reads out the ES1, with a location specified by the ES1 readout pointer, as a start point, and sends the ES1, thus read out, to the source of the request. The ES1 readout control unit then updates the ES1 readout pointer and the data leading end pointer.

Abstract: At step S372, permission information about video data that are being reproduced is obtained from permission information that represents whether video data corresponding to encoded video data equal to or larger than an access unit are permitted to be secondarily used. At step S373, it is determined whether the video data that are being reproduced have been permitted to be secondarily used corresponding to the permission information. When it has been determined that the video data that are being reproduced have been permitted to be secondarily used, at step S376, the video data that are being reproduced are captured. At step S381, a process using the captured video data is executed. The present invention can be applied to for example a game device that uses a DVD.

Abstract: A timing circuit has a bit line isolation signal input from one input terminal, and controls a timing to output the bit line isolation signal to a memory mat using an external signal input from the other input terminal. Thus, by controlling an operation timing of the bit line isolation signal with the external signal, an effect of a short circuit of a word line and a bit line caused on one memory cell array will be communicated also to the other memory cell array, and a defective bit line on the opposite sides of a shared sense amplifier can be detected.

Abstract: A clamp circuit and a high-voltage detection circuit are supplied with voltages from different power-supplies respectively. At a normal mode, the clamp circuit and the high-voltage detection circuit are supplied with a voltage of almost the same voltage level. At transition to the test mode, only the voltage supplied to the clamp circuit is increased to activate the high-voltage detection circuit.

Abstract: A pump circuit forming a boosted power supply (Vpp) generating circuit includes: first and second pumps generating a boosted power supply; and a test circuit controlling levels of stress applied to the first and second pumps in accordance with a signal input from a ring oscillator and a test signal. A semiconductor memory device of the present invention enables application of a desired level of stress to each capacitor of the pump circuit formed for a stress test, and provides enhanced efficiency of the stress test and increased reliability of the semiconductor integrated circuit.

Abstract: A pump circuit forming a boosted power supply (Vpp) generating circuit includes: first and second pumps generating a boosted power supply; and a test circuit controlling levels of stress applied to the first and second pumps in accordance with a signal input from a ring oscillator and a test signal. A semiconductor memory device of the present invention enables application of a desired level of stress to each capacitor of the pump circuit formed for a stress test, and provides enhanced efficiency of the stress test and increased reliability of the semiconductor integrated circuit.

Abstract: A semiconductor integrated circuit includes: first and second counters activated upon receipt of a low level signal and outputting a signal with a period which is twice that of the signal input; first fuse circuits connected to first counters; and a second fuse circuit connected to second counter. First counters are inactivated when fuses included in first fuse circuits are disconnected, and second counter is activated when a fuse included in second fuse circuit is disconnected. Thus, the period of a signal for determining a refresh period can be efficiently adjusted. Here, the arrangement of first fuse circuits and a second fuse circuit can be converse.

Abstract: A DRAM includes a control circuit for stopping an operation of increasing a potential of a Vpp line by a first pump under a self refresh mode.

Abstract: A refresh operation is started in response to activation of a refresh control signal. The refresh control circuit controls activation of a refresh control signal in accordance with a signal level of a row address decode enable signal in addition to signal levels of control signals activated in response to activation of signals /CAS and /RAS necessary for detecting the start of a CBR refresh operation. The row address decode enable signal is an internal control signal activated upon activation of a signal /RAS and maintained in an active state until signal /RAS is inactivated. As a result, the refresh control signal is not erroneously activated during normal operation even when a noise is caused to signal /RAS.

Abstract: A semiconductor memory device includes a control circuit, a test mode control circuit, an internal period setting circuit and an address latch circuit. The control circuit detects whether test mode is designated or not. The test mode control circuit detects whether or not self disturb test mode is designated. The internal period setting circuit repeatedly generates a clock signal of a prescribed period when the test mode and the self disturb test mode are designated. Simultaneously, the address latch circuit latches an address at a fall of a row address strobe signal. The row decoder is activated in response to the clock signal, and repeatedly sets the word line corresponding to the latched address to the selected state.

Abstract: A first logic gate circuit receives an internal row strobe signal, an internal column strobe signal and a self refresh mode for providing an operation state detection signal. The operation state detection signal attains an H level when in a stand-by state and a self refresh state. A second CMOS logic gate circuit is closed when the operation state detection signal attains an H level. Therefore, an external input/output control signal is not transmitted to the internal circuit, and a through current does not flow in the CMOS logic gate independent of the level of the external input/output control signal.

Abstract: When a pad is connected to ground and a mode switching signal MHYP attains an L level, an integrated semiconductor device attains an FP mode. Following the transition of an internal column address strobe signal ZCASF and an internal write enable signal ZWEF to an L level, an NOR gate is opened to allow entry of internal data. When the pad is connected to a power supply potential and the mode selecting signal MHYP attains an H level, the integrated semiconductor device attains an EDO mode. The NOR gate is opened when the internal row address strobe signal ZRASF attains an L level, whereby the external data is entered. The writing operation in an EDO mode can be increased in speed.