Patents by Inventor GOROU MORI

GOROU MORI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160282417
    Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.
    Type: Application
    Filed: June 8, 2016
    Publication date: September 29, 2016
    Inventors: Akira KAWABE, Gorou MORI
  • Patent number: 9389277
    Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akira Kawabe, Gorou Mori
  • Publication number: 20160172717
    Abstract: A battery assembly controller controls terminal voltages of a plurality of series-connected secondary batteries to be equal. The controller includes a discharge circuit selectively reducing the terminal voltages of the secondary batteries; and a monitoring circuit directly connected to positive and negative electrodes of the secondary batteries to monitor the terminal voltages of the secondary batteries.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventors: Junji NAKATSUKA, Gorou MORI
  • Publication number: 20150155735
    Abstract: A battery device includes: a secondary battery; a charger; a first transistor configured to control conduction between the secondary battery and a load; a second transistor configured to control conduction between the charger and the secondary battery; diodes of which cathodes are connected to each other and that are connected between the secondary battery and the charger; a capacitor configured to accumulate charge to be transferred to the gate of the first transistor; a capacitor configured to accumulate charge to be transferred to the gate of the second transistor; and a battery control device configured to control charging/discharging of the secondary battery.
    Type: Application
    Filed: February 6, 2015
    Publication date: June 4, 2015
    Inventors: Gorou MORI, Fumihito INUKAI, Toshinobu NAGASAWA
  • Publication number: 20140111216
    Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 24, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Akira KAWABE, Gorou MORI
  • Publication number: 20110241920
    Abstract: Provided is a resistive digital-to-analog converter capable of reducing a digital-to-analog conversion error caused by a change of the on-resistance of a transistor. On-resistance correcting PMOS transistors Q2 to Q2N?1 or on-resistance correcting NMOS transistors Q2? to Q2N?1? are respectively connected in parallel to at least one of switching MOS transistors Q1 and Q1? in each of switch circuits S1 to S2N?1. Each of the on-resistance correcting PMOS transistors and the on-resistance correcting NMOS transistors is connected to correct the change of the on-resistance occurring with a change of an analog signal caused by a change of a multi-bit digital input signal. The on-resistance correcting PMOS transistors Q2 to Q2N?1 or the on-resistance correcting NMOS transistors Q2? to Q2N?1? are switched on or off in conjunction with switching of the switching MOS transistors Q1 and Q1? according to the change of the digital input signal.
    Type: Application
    Filed: June 14, 2011
    Publication date: October 6, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: GOROU MORI