Patents by Inventor Gotaro TAKEMOTO

Gotaro TAKEMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11626479
    Abstract: A semiconductor device includes: a semiconductor base substrate including a semiconductor layer; a first main electrode; a second main electrode; a plurality of peripheral trenches formed on a surface of the semiconductor layer and having bottom portions covered by the semiconductor layer in a peripheral region; and a plurality of in-trench electrodes each embedded in each of the plurality of peripheral trenches byway of an insulation layer formed on an inner surface of the each peripheral trench, wherein the semiconductor base substrate further includes, in the peripheral region, a plurality of second conductive type floating regions disposed in the semiconductor layer at a depth position deeper than the bottom portions of the peripheral trenches in a spaced apart manner from the peripheral trenches and having a potential in a floating state.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: April 11, 2023
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Gotaro Takemoto, Toshihiro Okuda, Mizue Kitada
  • Publication number: 20200388671
    Abstract: A semiconductor device includes: a semiconductor base substrate including a semiconductor layer; a first main electrode; a second main electrode; a plurality of peripheral trenches formed on a surface of the semiconductor layer and having bottom portions covered by the semiconductor layer in a peripheral region; and a plurality of in-trench electrodes each embedded in each of the plurality of peripheral trenches byway of an insulation layer formed on an inner surface of the each peripheral trench, wherein the semiconductor base substrate further includes, in the peripheral region, a plurality of second conductive type floating regions disposed in the semiconductor layer at a depth position deeper than the bottom portions of the peripheral trenches in a spaced apart manner from the peripheral trenches and having a potential in a floating state.
    Type: Application
    Filed: June 4, 2020
    Publication date: December 10, 2020
    Inventors: Gotaro TAKEMOTO, Toshihiro OKUDA, Mizue KITADA
  • Publication number: 20200295179
    Abstract: A semiconductor device includes: a gate electrode disposed in the inside of a trench via a gate insulating film; a shield electrode positioned between the gate electrode and a bottom of the trench; an electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along a side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n+-type source region, and electrically connected to the shield electrode on both end portions of the trench as viewed in a plan view, wherein the shield electrode has high resistance regions positioned at both end portions of the trench as viewed in a plan view, and a low resistance region positioned at a position sandwiched by the high resistance regions.
    Type: Application
    Filed: January 14, 2016
    Publication date: September 17, 2020
    Inventors: Masato KISHI, Toshiyuki TAKEMORI, Toshitaka AKIMOTO, Gotaro TAKEMOTO, Eiki ITO