Abstract: A liquid cooling device comprises a heat spreader disposed along a plurality of memory modules on a dual in-line memory module (DIMM), a cold rail block extending along the heat spreader and a compressible thermal adapter interleaved between the cold rail block and the memory modules. The thermal adapter is compressible in a direction perpendicular to the plane of the DIMM board, thus allowing the components of the cooling device to be moved and adjusted relative to each other in a direction perpendicular to the plane of the DIMM. In a preferred embodiment, matching smooth surfaces of adjacent components within the cooling device are collated with a lubricant, thus permitting a low-friction gliding of these components relative to each other and allowing the DIMM to be easily removed from the cooling device and to be replaced without effort and without tooling.

Abstract: A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

Abstract: A system for cooling processor assembly is disclosed which comprises a printed circuit board (PCB) with a plurality of heat emitting electronic components and a housing for each PCB with a heat collector. The heat collector is constructed in one-piece material covering the plurality of heat emitting electronic components through heat collecting areas with different heights adapted to the different heights of the electronic components as regard to the PCB surface wherein the heat collecting areas being in thermal contact with the electronic components.

Abstract: A switching device is able to route the arriving data packets according to data packet destination information to dedicated output ports. The switching arrangement has, for each set of input ports in the switching device, a set of output buffers with an output buffer for storing the payload of each data packet at an address in the output buffer which pertains to the same set of output buffers and belongs to the dedicated output ports. At least one of the output buffers has a set of output queues with an output queue for each output port for storing the address of each payload stored in the corresponding output buffer. An arbiter controls a readout order of the stored addresses. For the output buffers which pertain to the same set of output ports a multiplexer multiplexes according to the readout order the payloads from the output buffers to the output ports.

Abstract: A system for cooling processor assembly is disclosed which comprises printed circuit boards (PCB) with a plurality of heat emitting electronic components, and a housing for each PCB with a heat sink covering at least partly the heat emitting electronic components. The housing comprises a base portion to which are transferred heat emitted by the electronic components. Furthermore, the system for cooling processor comprises a cooling plate on which are fixed in series the different PCBs by directly positioning the base portion of the housings onto the cooling plate. The housings for each PCB system include at their base portions clamps to be inserted into corresponding guiding holes of the cooling plate when a PCB together with its housing is positioned onto the cooling plate at a specific therefor dedicated place defined by the guiding holes.

Abstract: A system for cooling processor assembly is disclosed which comprises printed circuit boards (PCB) with a plurality of heat emitting electronic components, and a housing for each PCB with a heat sink covering at least partly the heat emitting electronic components. The housing comprises a base portion to which are transferred heat emitted by the electronic components. Furthermore, the system for cooling processor comprises a cooling plate on which are fixed in series the different PCBs by directly positioning the base portion of the housings onto the cooling plate. The housings for each PCB system include at their base portions clamps to be inserted into corresponding guiding holes of the cooling plate when a PCB together with its housing is positioned onto the cooling plate at a specific therefor dedicated place defined by the guiding holes.

Abstract: A system for cooling processor assembly is disclosed which comprises a printed circuit board (PCB) with a plurality of heat emitting electronic components and a housing for each PCB with a heat collector. The heat collector is constructed in one-piece material covering the plurality of heat emitting electronic components through heat collecting areas with different heights adapted to the different heights of the electronic components as regard to the PCB surface wherein the heat collecting areas being in thermal contact with the electronic components.

Abstract: Discloses a switching arrangement for packets of data, with several input ports and several output ports and which is determined for the transportation of incoming packets to one or more designated of the output ports and from there to a subsequent device. More particularly it relates to a switching arrangement and method wherein for each input port a set of output buffers is arranged, each set comprising an output buffer for each output port.

Abstract: A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.

Abstract: The present invention relates to a buffered crossbar switch which provides a step of changing the size and/or number of queuing buffer entries to ensure optimum buffer memory usage independent of the size of data packets processed.

Abstract: A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.

Abstract: The present invention relates to switching technology in computer networks and in particular to a method and system for switching information packets through a m input, n output device. According to the invention it is proposed to temporarily buffer said packets according to a new, self-explanatory, preferred a linear addressing scheme in which a respective buffer location of consecutive stream packets results from a respective self-explanatory, or linear, respectively, incrementation of a buffer pointer. Preferably, a matrix of FIFO storage elements (10,11,12,13) having an input and an output crossbar can be used for implementing input/output paralleling modes (ILP,OLP) and multiple lanes and achieving address input/output scaling up to a single cycle.

Abstract: A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Abstract: The present invention relates to switching technology in computer networks and in particular to a method and system for switching information packets through a m input, n output device. According to the invention it is proposed to temporarily buffer said packets according to a new, self-explanatory, preferred a linear addressing scheme in which a respective buffer location of consecutive stream packets results from a respective self-explanatory, or linear, respectively, incrementation of a buffer pointer. Preferably, a matrix of FIFO storage elements (10,11,12,13) having an input and an output crossbar can be used for implementing input/output paralleling modes (ILP,OLP) and multiple lanes and achieving address input/output scaling up to a single cycle.

Abstract: A method and means for exchanging messages between a multitude of computer systems is provided, whereby the sender system's memory is used as a buffer for the message to be transferred. The method comprises a first step of writing data into a portion of the sender system's memory, a second step of setting an indication signal in the receiver system, and a third step of performing a remote read access to the data in the sender system's memory. Thus, the message buffers of prior art solutions have been replaced by portions of the sender system's memory. The remote read access is performed by a direct memory adapter (DMA) in the receiver system, whereby said indication signal is mapped to the start address of said portion of the sender system's memory. Because any write access to a remote system's memory is forbidden, data integrity is preserved.

Abstract: An apparatus and method for controlling and rectifying possible metastability situations having a first circuit with a first clock signal (CLOCK1) at a first clock rate and a second circuit with a second clock signal (CLOCK2) at a second clock rate, the second circuit having an input circuit coupled to the first circuit and receiving signals therefrom. A control circuit for controlling possible metastability situations arising in communication between the first circuit and the second circuit is also provided. The control circuit receives as input the first clock signal and the second clock signal and provides a shifting of at least one of the two clock signals, in such a way that a possible metastable state of the input circuit is avoided.

Abstract: A computer system with a coupling facility is provided with a plurality of processors and a plurality of intersystem channels coupled to the processors via a memory bus. The coupling facility includes a memory bus interface for the memory bus and a plurality of channels for coupling said channels to said processors. The memory bus interface includes an adapter with at least two hardware vectors provided for command detection, command isolation, and parallel testing of the error states of the intersystem channels, one which detects a command vector arrival, and a second which contains error state vector indicators. A LOCATE CHANNEL BUFFER (LCB) instruction is employed which performs a sense and reset operation on the command vector to identify and isolate a new command, and subsequently reads a vector of said error states vector indicator to determine the presence or absence of link errors.

Abstract: The invention concerns the transfer of data information in a multiprocessor computer system. If data information has to be transferred between two processor units then the associated control information is made available on a connection bus and the data information is transferred afterwards via a switch unit from the first to the second processor unit. If however data information is to be transferred from a sending processor unit to all other processor units (broadcast transfer) then not only is control information transferred via the connection bus but subsequent data information too; a transfer of data information via the switch unit does not occur in this case. In this manner it is possible to reduce the outlay for the switch unit in terms of circuitry and programming.

Abstract: A type band for a printer comprises a track of marks to be scanned (timing marks) at least one of which is obliquely positioned relative to its adjoining marks. The centers of all marks are equidistantly spaced. When the horizontally moving type band is vertically displaced, the time spacing of the scanning signal of the obliquely positioned timing mark is changed over the scanning signal of its adjacent timing mark. The magnitude of the vertical displacement of the type band is derived from the change in this time spacing. The displacement data thus obtained permit compensating for the vertical displacement of the type band (using, for instance, a stepper motor).

Abstract: To obtain a good print quality in metal paper printers, the print current, after ignition of the arc, must be rapidly reduced to a fraction of the value necessary for ignition. For this purpose, two transistor power stages (T3, T4) are connected to the print electrode (2). Their partial currents form the print current, whose rapid reduction after ignition of the arc is obtained by the two transistor power stages being operated at voltages (U2, U3) of different magnitude. The second transistor stage (T4) is operated at a voltage (U3), whose magnitude corresponds to the drop in potential occurring upon ignition between the grounded metal layer (3) of the record carrier (4) and the print electrode. As a result, the second transistor stage is switched off when a diode (D) connected to it becomes non-conductive.