Abstract: The present invention relates to a buffered crossbar switch which provides a step of changing the size and/or number of queuing buffer entries to ensure optimum buffer memory usage independent of the size of data packets processed.

Abstract: A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Abstract: A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Abstract: A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.

Abstract: The present invention relates to a buffered crossbar switch and its method of operation which provides a step of changing the size and/or number of queuing buffer entries to ensure optimum buffer memory usage independent of the size of data packets processed.

Abstract: The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein information packets of p different priority levels are routed from said n input ports (i—0, . . . , i_n-1) to said m output ports (o—0, . . . , o_m-1). Within said control logic (2), a pool (CRA) of buffers (CRA—0, CRA—1, . . . ) is provided for each crosspoint (4) for temporarily storing address information related to said information packets.

Abstract: The present invention relates to a method of operating a buffered crossbar switch. The proposed method reduces power dissipation in a buffered crossbar switch by reducing the number of crossbar buffer write processes.

Abstract: The present invention relates to a method of operating a crossbar switch (1) having a control logic (2) and n input ports (i—0, . . . , i_n-1) and m output ports (o—0, . . . , o_m-1), wherein information packets of p different priority levels are routed from said n input ports (i—0, . . . , i_n-1) to said m output ports (o—0, . . . , o_m-1). Within said control logic (2), a pool (CRA) of buffers (CRA—0, CRA—1, . . . ) is provided for each crosspoint (4) for temporarily storing address information related to said information packets.

Abstract: The basic idea comprised of the present invention is to decentralize the generation of time information without suffering from the cost disadvantages expectable due to use of prior art techniques necessary for synchronizing and correcting a plurality instead of only one or two of time suppliers caused by said decentralization. This is achieved by the approach not to readjust the oscillator(s), but, instead, to accept the inaccuracy of the physical device ‘oscillator’ but to measure its inaccuracy and to correct it with the aid of a continuos correction calculation which is advantageously done in a digital way under usage of ETS input information and system oscillator output information.

Abstract: A system and method for observing the two clocking phase signals, finding a point in time when said signals have a phase coincidence which is good enough for fulfilling a phase difference requirement (e.g. 20 ps), and switching from one clock source to the other. The essential idea is not to compare the phases directly but to generate an auxiliary signal out of the two clock signals which is easier to handle in order to find that desired point in time and which reflects all desired properties of the time dependent phase shift between said clock signals. At a predetermined location in the cycle of both clock signals (e.g. its positive transition) a pulse is generated out of each of the clock signals with matched identical delay elements located very close to each other on the same chip for both signals. As they match they produce exactly the same pulse widths. The absolute length of the pulse width is of minor relevance as long as the length of the pulses is the same within close limits.

Abstract: The exchange of commands and data between I/O devices, such as DASDs, and a computer system, preferrably a multiprocessor computer system, usually takes place via I/O adapters. The question arises of how to couple these I/O adapters to the computer system. In prior art solutions, the I/O adapters were either attached to the second level cache or to a memory bus. The present invention relates to a method of coupling the stream of I/O commands and I/O data to the computer system via the processor busses. Because of the high bandwidth of the processor busses, an additional transmission of I/O data does not disturb regular data traffic on the processor bus. One advantage of using the processor busses for the transmission of I/O data is that pins of the second level cache chips don't have to be used for the attachment of I/O adapters any more and thus become available for other purposes.

Abstract: A method for improved use of bandwidth on a bus. A bus, such as a processor bus between a processor and an L2 cache, is established having two states: a first state in which one half of the bus allows transmission in one direction and the other half allows transmission in the opposite direction; and a second state in which the entire bus bandwidth comprising both bus halves allow transmission in one direction. To achieve this bus design, means are provided for selectively switching at least one of the bus halves' transmission directions.

Abstract: Information about the relative phase relationship of the clocks of two chips that are connected with an inter-chip connection is used to adjust the clocks. In the method proposed by the invention, transitions between a good data transfer behaviour to a worse data transfer behaviour are detected as a function of the variable clock delays which delay the chip clock, and a clock delay value between the transitions is chosen. Thus, an optimization of data transmission is achieved, and it can be shown that with this procedure, the clock skew is accurately compensated as well. Additionally, a method for quantifying the variable clock delay, which consists of a multitude of delay elements arranged in a delay chain, is given. In order to do this, the number of delay elements necessary for a delay of half a clock cycle is determined. Thus, a connection between the length of a clock cycle and the delay caused by one delay element is established.

Abstract: Computer system processing complexes which can operate actually or apparently synchronously and in parallel or asynchronously in a network have a coupling facility for sending and receiving commands, responses, and data. The memory for the central processing complexes (which is accessible to each of the processing elements) is provided with storage for messages and data for coupling over a communication channel interface. Each of a plurality of processing elements (CPC) has data objects used to maintain state information for shared data in the coupling facility storage. The coupling facility can receive both message commands and data, sending data and responses to messages, and sending and receiving secondary messages.