Abstract: The present invention relates to a control circuit adapted for CMOS implementation for the control of the supply voltage for integrated circuits, and particularly, relates to the indication of and/or control of variations of a supply voltage from a predetermined value.

Abstract: A circuit arrangement includes a MOS field effect transistor as a variable resistance in series with a load such as an integrated circuit across a power supply with means for controlling the variable resistance to establish a very constant supply or input voltage to the load. A switch may be included to apply a constant supply or input voltage of different known values to a load such as an oscillator requiring different voltages at different stages of operation.

Abstract: A circuit arrangement and process is provided for converting an analogue signal into a digital signal or converting a digital signal into an analogue signal. The circuit arrangement has first and second capacitances with a charge transfer device between the capacitances for providing a stepped exchange of charge therebetween. For analogue to digital conversion, a device is provided which brings the second capacitance to a given charge state for each step exchange. An evaluation device evaluates the charge state of the second capacitance for each stepped exchange until the charge on the second capacitance is below a given level. A counting device counts each of the stepped exchanges of charge such that the total count provides the corresponding digital signal. For digital to analogue conversion, in one embodiment a charge is placed on the second capacitance. The charge transfer device then removes equal quantities of charge in a plurality of steps and transfers this charge to the first capacitance.

Abstract: Regenerating amplifier for use with two charge coupled devices comprising field effect transistors to pre-charge the output diffusion capacitance of an output charge coupled device and the input diffusion capacitance of an input charge coupled device. The output diffusion capacitance is discharged by the arrival of output charge, in turn holding off an input gate such that the charge on the input diffusion capacitance is not shifted into the input charge coupled device. Various embodiments having control potentials and a field effect transistor to fully discharge the input diffusion capacitance of an input charge coupled device being usable with a plurality of input charge coupled devices having corresponding output charge coupled devices wherein individual charging transistors are available to charge each output diffusion zone capacitance with a common transistor being used to charge all input diffusion capacitances.

Abstract: Regenerator circuit for CCD elements in which charge representing information is transferred from a first CCD element to a second CCD element. The circuit includes a first MOS capacitance and a second capacitance connected in series with the first capacitance, the point at which the two capacitances are connected with one another being connected to the input of said second CCD. The output of the first CCD includes an output stage having an output diffusion zone. A transistor is connected between a terminal to which a potential .phi..sub.v can be connected and the point between said first and second capacitances. This transistor has a gate electrode which is connected by a line to the output diffusion zone of the first CCD.

Abstract: A compensation element and method for operating the same, for use with dynamic semiconductor stores, employing a main storage element operatively connected to a word line and a bit line, and an evaluator circuit operatively connected to the bit line, by means of which the storage element may be read out, comprising the steps of capacitively coupling a correcting voltage to the bit line which may be selectively applied thereto in response to signals on a compensation-selector line operative to control the application of said correcting voltage to the bit line whereby the same is raised to the most favorable middle potential of U.sub.BD =0.5 (U.sub.BO + U.sub.Bl), in which U.sub.BO = read outvoltage resulting from storage of a binary "0", and U.sub.Bl = read out voltage resulting from storage of a binary "1".