Patents by Inventor Gou Fukano

Gou Fukano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200160912
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Application
    Filed: January 24, 2020
    Publication date: May 21, 2020
    Inventor: Gou FUKANO
  • Patent number: 10580493
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Gou Fukano
  • Publication number: 20190206493
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 4, 2019
    Inventor: Gou FUKANO
  • Patent number: 10276240
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Gou Fukano
  • Publication number: 20180268904
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Application
    Filed: May 21, 2018
    Publication date: September 20, 2018
    Inventor: Gou FUKANO
  • Patent number: 10008268
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Gou Fukano
  • Publication number: 20170229181
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventor: Gou FUKANO
  • Patent number: 9666284
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 30, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gou Fukano
  • Publication number: 20160254055
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Application
    Filed: May 11, 2016
    Publication date: September 1, 2016
    Inventor: Gou FUKANO
  • Patent number: 9368213
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: June 14, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gou Fukano
  • Publication number: 20150294722
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 15, 2015
    Inventor: Gou FUKANO
  • Patent number: 9053765
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gou Fukano
  • Publication number: 20140084353
    Abstract: A nonvolatile semiconductor memory device with a first region including a memory cell array of a plurality of memory cells arrayed in three dimensions and a second region with a peripheral circuit for controlling the memory cell array is described. The peripheral circuit includes an insulating film and a template region. The template region has a length and a width and the insulating film is spaced from (does not overlap) the edges of the template region and is arranged in the template region so that a coverage ratio of the template region is at least above a minimum coverage ratio of 30-50%. Satisfying the minimum coverage ratio allows the device layers above the second region to be formed with sufficient flatness to allow the memory device to be functional.
    Type: Application
    Filed: March 4, 2013
    Publication date: March 27, 2014
    Inventor: Gou FUKANO
  • Publication number: 20140086001
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.
    Type: Application
    Filed: March 4, 2013
    Publication date: March 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Gou FUKANO
  • Patent number: 8437170
    Abstract: According to one embodiment, a semiconductor storage device includes memory cells including serially-connected variable-resistance layer and diode. A memory cell array includes the memory cells arranged on a plane including a first and second axes and has a first region lying along an edge of the array and a second region lying opposite to the edge with respect to the first region. A first wiring is continuous along the first axis between both ends of the array, partly lies in the second region, and is connected to the first ends of the memory cells. A second wiring lies along the first axis only in the first region, is connected to the first ends of the memory cells, and is divided between adjacent memory cells. A third wiring is continuous along the second axis between both ends of the array, and connected to the second ends of the memory cells.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gou Fukano
  • Patent number: 8295070
    Abstract: According to one embodiment, a resistance change memory includes a stacked layer structure stacked on a semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . a n-th conductive line, a n-th variable resistance element and a (n+1)-th conductive line, where n is a natural number equal to or larger than 2, and a first to a n-th drivers which drives the first to the (n+1)-th conductive lines. The odd-numbered conductive lines are extends in a first direction along a surface of the semiconductor substrate. The even-numbered conductive lines are extends in a second direction along the surface of the semiconductor substrate. Sizes of the first to (n+1)-th drivers become large gradually from the first driver to the (n+1)-th driver.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: October 23, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gou Fukano
  • Publication number: 20120049148
    Abstract: According to one embodiment, a three-dimensional nonvolatile semiconductor memory includes a semiconductor substrate, a memory cell array includes memory cells stacked on the semiconductor substrate and first conductive layers connected to the memory cells, a dummy stacked layer structure includes second conductive layers stacked on the semiconductor substrate, and surrounding the memory cell array, and a metal layer provided on the memory cell array and the dummy stacked layer structure. The second conductive layers are fixed on a ground potential.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 1, 2012
    Inventor: Gou FUKANO
  • Publication number: 20110164444
    Abstract: According to one embodiment, a resistance change memory includes a stacked layer structure stacked on a semiconductor substrate in order of a first conductive line, a first variable resistance element, a second conductive line, a second variable resistance element, . . . a n-th conductive line, a n-th variable resistance element and a (n+1)-th conductive line, where n is a natural number equal to or larger than 2, and a first to a n-th drivers which drives the first to the (n+1)-th conductive lines. The odd-numbered conductive lines are extends in a first direction along a surface of the semiconductor substrate. The even-numbered conductive lines are extends in a second direction along the surface of the semiconductor substrate. Sizes of the first to (n+1)-th drivers become large gradually from the first driver to the (n+1)-th driver.
    Type: Application
    Filed: December 15, 2010
    Publication date: July 7, 2011
    Inventor: Gou FUKANO
  • Publication number: 20110063889
    Abstract: According to one embodiment, a semiconductor storage device includes memory cells including serially-connected variable-resistance layer and diode. A memory cell array includes the memory cells arranged on a plane including a first and second axes and has a first region lying along an edge of the array and a second region lying opposite to the edge with respect to the first region. A first wiring is continuous along the first axis between both ends of the array, partly lies in the second region, and is connected to the first ends of the memory cells. A second wiring lies along the first axis only in the first region, is connected to the first ends of the memory cells, and is divided between adjacent memory cells. A third wiring is continuous along the second axis between both ends of the array, and connected to the second ends of the memory cells.
    Type: Application
    Filed: August 26, 2010
    Publication date: March 17, 2011
    Inventor: Gou FUKANO
  • Patent number: 7907439
    Abstract: A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a plurality of bit line gates provided between the cell arrays and each operative to establish a connection between the bit lines in adjacent cell arrays; and a controlling circuit operative to form a data transfer path via the connection between the bit lines formed through the bit line gate when the controlling circuit accesses to the memory cell.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: March 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Kushida, Gou Fukano