Patents by Inventor Gou Tamura

Gou Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6529411
    Abstract: A reference voltage generator circuit comprises a band gap circuit and a level correction regulator circuit. The band gap circuit generates output voltages REF 1, REF 2 having temperature dependence according to each of the write/erase mode and verify/read mode by setting the resistance values of resistors, and one of the output voltages is selected by a transfer gate and is regarded as REF. The level correction regulator circuit generates, based on the output REF, an output voltage OUT (reference voltage) on a level which is required for each mode. By virtue of the above construction, a level correction regulator circuit and one band gap circuit can constitute a reference voltage generator circuit for a nonvolatile memory which can realize temperature characteristics according to each mode while reducing the layout area.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: March 4, 2003
    Assignee: NEC Corporation
    Inventors: Yasuhiro Tonda, Gou Tamura
  • Publication number: 20020086474
    Abstract: A reference voltage generator circuit comprises a band gap circuit and a level correction regulator circuit. The bard gap circuit generates output voltages REF 1, REF 2 having temperature dependence according to each of write/erase mode and verify/read mode by setting the resistance values of resistors, and one of the output voltages is selected by a transfer gate and is regarded as REF. The level correction regulator circuit generates, based on the output REF, an output voltage OUT (reference voltage) on a level which is required for each mode. By virtue of the above construction, a level correction regulator circuit and one band gap circuit can constitute a reference voltage generator circuit for a nonvolatile memory which can realize temperature characteristics according to each mode while reducing the layout area.
    Type: Application
    Filed: November 29, 2001
    Publication date: July 4, 2002
    Inventors: Yasuhiro Tonda, Gou Tamura