Patents by Inventor Gou Uesono

Gou Uesono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Epitaxial silicon wafer having reduced stacking faults
    Patent number: 9755022
    Abstract: An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m?·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 5, 2017
    Assignees: SUMCO TECHXIV CORPORATION, SUMCO CORPORATION
    Inventors: Tadashi Kawashima, Naoya Nonaka, Masayuki Shinagawa, Gou Uesono
  • Method for growing an epitaxial film on a phosphorous-doped silicon wafer
    Patent number: 9425264
    Abstract: A method includes: a backside-oxidation-film-formation step in which an oxidation film is formed on a backside of a silicon wafer; a backside-oxidation-film-removal step in which the oxidation film provided at an outer periphery of the silicon wafer is removed; an argon-annealing step in which the silicon wafer after the backside-oxidation-film-removal step is subjected to a heat treatment in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; and an epitaxial-film-formation step in which an epitaxial film is formed on a surface of the silicon wafer after the argon-annealing step.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: August 23, 2016
    Assignees: SUMCO CORPORATION, SUMCO TECHXIV CORPORATION
    Inventors: Tadashi Kawashima, Naoya Nonaka, Masayuki Shinagawa, Gou Uesono
  • MANUFACTURING METHOD OF EPITAXIAL SILICON WAFER, AND EPITAXIAL SILICON WAFER
    Publication number: 20150380493
    Abstract: An epitaxial silicon wafer includes a silicon wafer added with phosphorus so that resistivity of the silicon wafer falls at or below 0.9 m?·cm, an epitaxial film formed on a first side of the silicon wafer, and an oxidation film formed on a second side of the silicon wafer opposite to the first side, wherein an average number of Light Point Defect of a size of 90 nm or more observed on a surface of the epitaxial film is one or less per square centimeter.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 31, 2015
    Applicants: SUMCO CORPORATION, SUMCO TECHXIV CORPORATION
    Inventors: Tadashi KAWASHIMA, Naoya NONAKA, Masayuki SHINAGAWA, Gou UESONO
  • MANUFACTURING METHOD OF EPITAXIAL SILICON WAFER, AND EPITAXIAL SILICON WAFER
    Publication number: 20140001605
    Abstract: A method includes: a backside-oxidation-film-formation step in which an oxidation film is formed on a backside of a silicon wafer; a backside-oxidation-film-removal step in which the oxidation film provided at an outer periphery of the silicon wafer is removed; an argon-annealing step in which the silicon wafer after the backside-oxidation-film-removal step is subjected to a heat treatment in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; and an epitaxial-film-formation step in which an epitaxial film is formed on a surface of the silicon wafer after the argon-annealing step.
    Type: Application
    Filed: June 24, 2013
    Publication date: January 2, 2014
    Inventors: Tadashi Kawashima, Naoya Nonaka, Masayuki Shinagawa, Gou Uesono