Abstract: A configurable delay cell for an integrated circuit includes a CMOS inverter and first through fourth transistors. A drain of the third transistor is connected to a drain of the fourth transistor for generating an output signal. A connection between an output terminal of the CMOS inverter and a source of the first transistor, a connection between the output terminal of the CMOS inverter and a drain of the second transistor, and a connection between the source of the first transistor and the drain of the second transistor are configurable, using an electronic design automation (EDA) tool, for achieving first, second, third, fourth, and fifth delay values. The resulting delay value can be programmed by making changes only in one or more of the metal layers of the integrated circuit.

Abstract: A configurable delay cell for an integrated circuit includes a CMOS inverter and first through fourth transistors. A drain of the third transistor is connected to a drain of the fourth transistor for generating an output signal. A connection between an output terminal of the CMOS inverter and a source of the first transistor, a connection between the output terminal of the CMOS inverter and a drain of the second transistor, and a connection between the source of the first transistor and the drain of the second transistor are configurable, using an electronic design automation (EDA) tool, for achieving first, second, third, fourth, and fifth delay values. The resulting delay value can be programmed by making changes only in one or more of the metal layers of the integrated circuit.

Abstract: A two-input multiplexer includes first, second, and third CMOS inverters, a transmission gate, and a tri-state inverter. The first CMOS inverter receives a select signal and outputs an inverted select signal. The second CMOS inverter receives a first input signal and outputs an inverted first input signal. The transmission gate receives the select signal, the inverted first input signal, and the inverted select signal, and outputs the inverted first input signal. The tri-state inverter receives the second input signal, the inverted select signal, and the select signal, and generates an inverted second input signal. The third CMOS inverter receives one of the inverted first and second input signals, and outputs one of the first and second input signals, respectively.