Patents by Inventor Goutham RAMESH

Goutham RAMESH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12254432
    Abstract: A method of automating a workflow may include obtaining a completeness graph including conditions applied to attributes of an entity, determining that a missing attribute subset of the attributes lacks a corresponding value, determining that a condition corresponding to a missing attribute of the missing attribute subset is satisfied, and obtaining a value for the missing attribute. The value may be a result of performing a task in the workflow. The method may further include modifying a state of the entity by assigning the value to the missing attribute to obtain a modified state of the entity.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: March 18, 2025
    Assignee: Intuit Inc.
    Inventors: Aminish Sharma, Anushrut Gupta, Ashish Kumar Mishra, Goutham Kallepalli, Manish Ramesh Shah
  • Publication number: 20240297621
    Abstract: An example method includes switching a first multiplexer circuit associated with first delay circuitry from (a) a first sub-lookup table (LUT) of a first LUT of digital pre-distortion (DPD) corrector circuitry to (b) a first corresponding sub-LUT of a second LUT of the DPD corrector circuitry, the first sub-LUT associated with the first delay circuitry, the second LUT storing updated values to compensate for non-linearity of power amplifier circuitry of a transmitter including the DPD corrector circuitry. The method includes, based on a value of a counter being equal to a difference between (1) a first delay of the first delay circuitry and (2) a second delay of second delay circuitry, switching a second multiplexer circuit associated with the second delay circuitry from (a) a second sub-LUT of the first LUT to (b) a second corresponding sub-LUT of the second LUT, the second sub-LUT associated with the second delay circuitry.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 5, 2024
    Inventors: Jawaharlal Tangudu, Goutham Ramesh, Sarma Sundareswara Gunturi, Harsh Garg, Jaiganesh Balakrishnan, Mathews John, Sashidharan Venkatraman, Sanjay Pennam
  • Publication number: 20240291632
    Abstract: A receiver includes: a PHY layer, and a processor coupled to the PHY layer. The processor is configured to: receive a set of data bits from the PHY layer; compare the set of data bits to a sync header pattern; determine a mismatch metric responsive to the comparison and to an adjustable scaling factor, and execute link synchronization operations based on the mismatch metric.
    Type: Application
    Filed: February 24, 2023
    Publication date: August 29, 2024
    Inventors: Jaiganesh BALAKRISHNAN, Kandalla KRISHNA, Aravind VIJAYAKUMAR, Goutham RAMESH