Abstract: A method of constructing a lookup table for network switch includes the steps of snooping a communication channel in the network switch for lookup table information. Upon detection of lookup table information on the communication channel, the lookup table information transmitting the lookup table information to a remote system memory. This constructs a lookup table in the remote system memory.

Abstract: A method of processing DMA operations includes providing a DMA descriptor, with the DMA descriptor including a reload field therein. The DMA descriptor is then processed, and a location of a next DMA descriptor is identified based upon a condition of the reload field.

Abstract: A method of processing DMA operations includes providing a DMA descriptor, with the DMA descriptor including a reload field therein. The DMA descriptor is then processed, and a location of a next DMA descriptor is identified based upon a condition of the reload field.

Abstract: A method of processing DMA operations includes providing a DMA descriptor, with the DMA descriptor including a reload field therein. The DMA descriptor is then processed, and a location of a next DMA descriptor is identified based upon a condition of the reload field.

Abstract: An integrated computing system includes at least one processor formed on a substrate, wherein the processor operates at a processor rate. The integrated computing system further includes a global bus that is coupled to the at least one processor and is formed on the substrate. The global bus supports transactions (e.g., data, operational instructions, and/or control signaling conveyances) at a rate that is equal to or greater than the processing rate. The integrated computing system further includes a device gateway and memory gateway that are operably coupled to the global bus and formed on the substrate. The device gateway provides an interface for at least one device (e.g., internal or external) to the global bus. The memory gateway provides an interface between the global bus and memory.

Abstract: A method and apparatus for interfacing a bus with a plurality of input/output (I/O) devices includes steps for handling transactions to and from the I/O devices. Transactions from the I/O devices includes processing that begins by receiving the transactions, where each transaction is received at a rate corresponding to the providing I/O device. The processing continues by identifying, for each transaction, a corresponding section of memory for temporarily storing the transaction. The particular section of memory is identified based on the type of transaction and/or the identity of the I/O device. The processing then continues by storing each transaction in the identified section of memory when the section has an available entry. When the bus is available and a transaction has been selected, the selected transaction is provided to the bus at the rate of the bus.

Abstract: A method and apparatus for interfacing memory with a bus in a computer system includes processing that begins by receiving a transaction from the bus. The transaction may be a read transaction and/or a write transaction. Upon receiving the transaction, the process continues by validating the received transaction and, when valid, acknowledges its receipt. The processing then continues by storing the physical address, which was included in the received transaction, and the corresponding command in an address/control buffer. The processing continues by retrieving the physical address from the address/control buffer when the transaction is to be processed. The determination of when the transaction is to be processed is based on an ordering within the address/control buffer. The processing then continues by performing the transaction utilizing a first or second memory path based on the physical address, such that a first or second memory is accessed.

Abstract: A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and an common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit.