Patents by Inventor Govind Saraswat

Govind Saraswat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240119457
    Abstract: Methods and server systems for computing fraud risk scores for various merchants associated with an acquirer described herein. The method performed by a server system includes accessing merchant-related transaction data including merchant-related transaction indicators associated with a merchant from a transaction database. Method includes generating a merchant-related transaction features based on the merchant-related indicators. Method includes generating via risk prediction models, for a payment transaction with the merchant, merchant health and compliance risk scores, merchant terminal risk scores, merchant chargeback risk scores, and merchant activity risk scores based on the merchant-related transaction features. Method includes facilitating transmission of a notification message to an acquirer server associated with the merchant.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 11, 2024
    Applicant: MASTERCARD INTERNATIONAL INCORPORATED
    Inventors: Smriti Gupta, Adarsh Patankar, Akash Choudhary, Alekhya Bhatraju, Ammar Ahmad Khan, Amrita Kundu, Ankur Saraswat, Anubhav Gupta, Awanish Kumar, Ayush Agarwal, Brian M. McGuigan, Debasmita Das, Deepak Yadav, Diksha Shrivastava, Garima Arora, Gaurav Dhama, Gaurav Oberoi, Govind Vitthal Waghmare, Hardik Wadhwa, Jessica Peretta, Kanishk Goyal, Karthik Prasad, Lekhana Vusse, Maneet Singh, Niranjan Gulla, Nitish Kumar, Rajesh Kumar Ranjan, Ram Ganesh V, Rohit Bhattacharya, Rupesh Kumar Sankhala, Siddhartha Asthana, Soumyadeep Ghosh, Sourojit Bhaduri, Srijita Tiwari, Suhas Powar, Susan Skelsey
  • Patent number: 10599808
    Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: March 24, 2020
    Assignee: Oracle International Corporation
    Inventors: Govind Saraswat, Wai Chung William Au, Douglas Stanley, Anuj Trivedi
  • Publication number: 20190258773
    Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Inventors: Govind Saraswat, Wait Chung Williams Au, Douglas Stanley, Anuj Trivedi
  • Patent number: 10282507
    Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 7, 2019
    Assignee: Oracle International Corporation
    Inventors: Govind Saraswat, Wai Chung William Au, Douglas Stanley, Anuj Trivedi
  • Publication number: 20170147738
    Abstract: A method involves determining failure in time rate for a circuit. The method may include obtaining circuit data regarding a circuit. The circuit may include a first wire segment and a second wire segment. The method may further include obtaining reliability data. The reliability data may describe a failure of the circuit over a pre-determined time period. The method may further include obtaining a thermal map. The method may further include determining a first failure rate for the first wire segment of the circuit. The first failure rate may be a probability that the first wire segment fails in a predetermined amount of time. The method may further include determining a second failure rate for the second wire segment of the circuit. The method may further include generating a model of the circuit. The model of the circuit may describe the first and the second failure rate of the circuit.
    Type: Application
    Filed: November 24, 2015
    Publication date: May 25, 2017
    Inventors: Govind Saraswat, Wai Chung William Au, Douglas Stanley, Anuj Trivedi