Abstract: A method for forming a uniform damascene profile is provided. A wet etching process using a mixture containing ionized water, hydrochloric acid and hydrofluoric acid as an etching solution is applied on a substrate having a single/dual damascene structure formed thereon. The etching solution of the mixture containing ionized water, hydrochloric acid and hydrofluoric acid creates an etch selectivity between various layers of the single/dual damascene structure approximately 1:1. Thus, a damascene structure with a good profile is obtained.

Abstract: A polymer debris pre-cleaning method is described. The method provides a specific gas mixture after an etching process that uses a fluorocarbon reacting gas. The plasma generated from the gas mixture is then used to perform a pre-cleaning of the polymer debris. The gas mixture of specific gases is selected from the group of an oxygen and nitrogen gas mixture, a hydrogen and argon gas mixture, an argon and nitrogen gas mixture, or an oxygen and argon gas mixture. Since the plasma generated from the gas mixture softens, burns or even removes the hardened polymer debris, the polymer debris can be completely removed in the subsequent cleaning process. The duration of the subsequent cleaning process is thus reduced.

Abstract: A method of forming floating gates for flash memory is disclosed to improve contact properties with erase gates. The method includes formation of a tunnel oxide layer, a polysilicon layer and an interpoly insulating layer. These layers are patterned in two dry etching steps to complete floating gate definition. In the first etching step, the interpoly insulating layer is etched open in an oxide chamber to form a taper opening. The taper opening is further deepened in the second etching step, in which the polysilicon layer and the tunnel oxide layer are etched open in sequence in a poly chamber. A contact with smooth, vertical surface profile is thus formed in the second etching step. The two-step dry etching procedure is found to provide good contact profile for the floating gate to facilitate subsequent oxide deposition and contact filling. The proposed etching procedure also makes substantial operation reduction for floating gate formation and thus advantageously costs down for flash memory production.

Abstract: An etching process. The etching process comprises the steps of providing a substrate having an isolation region and a first conductive region and a second conductive region formed thereon. The second conductive region is higher than the first conductive region. An etching stop layer is formed over the substrate. A dielectric layer is formed on the etching stop layer. An etching process is performed with a mixture gas including CH2F2, C5F8, CO, O2 and Ar to form a first opening and a second opening in the dielectric layer, wherein the first opening exposes a portion of the first conductive region and a portion of the isolation region and the second opening exposes a portion of the etching stop layer over the second conductive region.

Abstract: A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening opening after the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses.

Abstract: A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening openingafter the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses.

Abstract: A method of forming a local interconnect contact opening is described. A liner layer is formed on a substrate having a gate structure, a first source/drain region, and a second source/drain region formed thereon. A planarized dielectric layer is formed over the liner layer. A photoresist layer, which defines the location of the local interconnect contact opening, is formed over the dielectric layer. A one-step etching process is performed using a C5F8/CO/O2/Ar etching gas and the liner layer as an etching stop. The dielectric layer exposed by the opening of the photoresist layer is removed to expose the liner layer. The liner layer and the photoresist layer are removed.