Abstract: A method for performing a cycle update on a RAID storage device by a storage system includes storing first data in a first buffer. The method additionally includes retrieving a command block associated with the first data, and executing the command block to perform a set of operations in a sequence specified by the command block. The set of operations includes reading second data from an address of the RAID storage device and generating redundant data based on the first data with the second data. The set of operations further includes storing the redundant data in a second buffer and writing the first data to the address of the RAID storage device when the RAID storage device is a data storage device, and writhing the redundant data stored in the second buffer to the address of the RAID storage device when the RAID storage device is a parity storage device.

Abstract: A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs hardware manipulation of CLs (Cache Lines), a hash table, and per array LRU queues.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages merging data with existing data on fast writes to storage write cache substantially without using firmware for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs writes to storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs cache line updates for writes, reads, and destages from storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs destage operations from storage write cache with minimal firmware involvement to enhance performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs data age identification in storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine manages cache line updates for purges from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.

Abstract: A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs a host read and a cache destage simultaneously from storage write cache substantially without firmware involvement for greatly enhancing performance.

Abstract: Methods and structure for formatting and processing Scatter Gather Lists (SGLs). One exemplary embodiment is a storage controller that includes a cache memory storing data for a logical volume, and a control unit. The control unit is able to service an Input/Output (I/O) request based on a Scatter Gather List (SGL) that refers to the cache memory, the SGL comprising multiple entries that each include a flag field and an identifier (ID) field. The entries are assigned to categories that are each associated with a different set of stored processing instructions. The control unit is able to identify a category for an entry based on a combination of both flag field and ID field for the entry, and the control unit is able to process the entry using the set of instructions associated with the identified category.

Abstract: Methods and structure for managing cache memory for a storage controller. One exemplary embodiment a Redundant Array of Independent Disks (RAID) storage controller. The storage controller includes an interface operable to receive Input/Output (I/O) requests from a host, a Direct Memory Access (DMA) module, a memory comprising cache data for a logical volume, and a control unit. The control unit is able to generate Scatter Gather Lists (SGLs) that indicate the location of cache data for incoming read requests. Each SGL is stored in the memory, and at least one SGL points to cache data that is no longer indexed by the cache. The control unit is also able to service an incoming read request based on the SGL, by directing the DMA module to transfer the cache data that is no longer indexed to the host.

Abstract: An interface receives a command corresponding to a non-volatile memory. The interface determines whether a bypass mode is enabled and whether the command is a medium-access command. A primary processing node processes the command in response to determining at least one of the following: that the bypass mode is disabled or that the command is not a medium-access command. A secondary processing node processes the command, in response to determining that the bypass mode is enabled and that the command is a medium-access command.

Abstract: A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.

Abstract: A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.

Abstract: A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.