Patents by Inventor Grégory Avenier
Grégory Avenier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817353Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.Type: GrantFiled: January 4, 2022Date of Patent: November 14, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Alexis Gauthier, Gregory Avenier
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Patent number: 11804521Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.Type: GrantFiled: January 26, 2022Date of Patent: October 31, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
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Patent number: 11776995Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.Type: GrantFiled: May 2, 2022Date of Patent: October 3, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
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Publication number: 20220254879Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.Type: ApplicationFiled: May 2, 2022Publication date: August 11, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
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Publication number: 20220254686Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Gregory AVENIER, Alexis GAUTHIER, Pascal CHEVALIER
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Patent number: 11355581Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.Type: GrantFiled: August 17, 2020Date of Patent: June 7, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
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Patent number: 11348834Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.Type: GrantFiled: June 23, 2020Date of Patent: May 31, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Gregory Avenier, Alexis Gauthier, Pascal Chevalier
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Publication number: 20220149151Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.Type: ApplicationFiled: January 26, 2022Publication date: May 12, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
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Publication number: 20220130728Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.Type: ApplicationFiled: January 4, 2022Publication date: April 28, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
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Patent number: 11276752Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.Type: GrantFiled: August 17, 2020Date of Patent: March 15, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
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Patent number: 11251084Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.Type: GrantFiled: June 23, 2020Date of Patent: February 15, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Alexis Gauthier, Gregory Avenier
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Publication number: 20210057521Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.Type: ApplicationFiled: August 17, 2020Publication date: February 25, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
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Publication number: 20210057520Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.Type: ApplicationFiled: August 17, 2020Publication date: February 25, 2021Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
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Publication number: 20200411382Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.Type: ApplicationFiled: June 23, 2020Publication date: December 31, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal CHEVALIER, Alexis GAUTHIER, Gregory AVENIER
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Publication number: 20200411381Abstract: A circuit includes at least one bipolar transistor and at least one variable capacitance diode. The circuit is fabricated using a method whereby the bipolar transistor and variable capacitance diode are jointly produced on a common substrate.Type: ApplicationFiled: June 23, 2020Publication date: December 31, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Gregory AVENIER, Alexis GAUTHIER, Pascal CHEVALIER
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Patent number: 10468508Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: GrantFiled: January 17, 2019Date of Patent: November 5, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
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Patent number: 10381269Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.Type: GrantFiled: March 5, 2018Date of Patent: August 13, 2019Assignee: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Gregory Avenier
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Publication number: 20190148531Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: ApplicationFiled: January 17, 2019Publication date: May 16, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Alexis GAUTHIER, Pascal CHEVALIER, Gregory AVENIER
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Patent number: 10224423Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.Type: GrantFiled: October 13, 2017Date of Patent: March 5, 2019Assignee: STMircoelectronics (Crolles 2) SASInventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
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Publication number: 20180197781Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.Type: ApplicationFiled: March 5, 2018Publication date: July 12, 2018Applicant: STMicroelectronics (Crolles 2) SASInventors: Pascal Chevalier, Gregory Avenier