Patents by Inventor Grace H. Ho

Grace H. Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • In-situ overlay alignment
    Patent number: 7218400
    Abstract: A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.
    Type: Grant
    Filed: March 3, 2004
    Date of Patent: May 15, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Grace H. Ho, Ming-Che Wu, Li-Heng Chou, Hung-Chang Hsieh, Jung Ting Chen, Yao-Ching Ku
  • Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer
    Patent number: 6821905
    Abstract: A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: November 23, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Shing-Chyang Pan, Shwang-Ming Jeng, Chen-Hua Yu, Grace H. Ho
  • Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer
    Publication number: 20040023497
    Abstract: A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.
    Type: Application
    Filed: July 30, 2002
    Publication date: February 5, 2004
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chyang Pan, Shwang-Ming Jeng, Chen-Hua Yu, Grace H. Ho