Abstract: A method and system for generating consumer interest in broadcast advertising that contains encoded advertising incentives. The method includes receiving content from a broadcast stream provider and using a decoder with a processor that executes a software program tool embodied therein. The processor of the decoder executes the steps of the software program tool to detect the presence of advertising incentives in the broadcast stream. The processor of the decoder detects and responds to commands from the control device to display details about the advertising incentive. The processor of the decoder sends notifications to the user, updates the user's calendar, and sends feedback to the advertiser that the advertisement was chosen and accepted by the user.

Abstract: An apparatus includes a flexible support member having a first and second ends and a plurality of guides there between. The apparatus further includes an electrical generator having a magnet, an electrical coil surrounding the magnet, and a pair of electrical leads for delivering electrical current generated in the coil. A tensile member is connected between the first end of the support member and the magnet, wherein the tensile member extends along a path from the first end of the support member through the plurality of guides to the magnet. A spring element biases the magnet in a direction to impart tension to the tensile member. Deflection of the support member from a relaxed position to a deflected position modifies the length of the path of the tensile member to displace the magnet within the electrical coil and generate an electrical current.

Abstract: Computer peripheral expansion apparatus, methods of operation, and computer program products including blade peripheral expansion units (‘BPEUs’), each BPEU including a peripheral interconnect multiplexer coupled for peripheral interconnect data communications through an upstream peripheral interconnect bus (‘PIB’) segment to a host blade, the upstream PIB segment fanned out by the multiplexer into two or more peripheral downstream interconnect channels, the multiplexer connecting the upstream PIB segment to only one of the downstream channels at a time; and the two or more downstream peripheral interconnect channels, at least one of the downstream channels connected to at least one peripheral interconnect device (‘PID’) in the BPEU, the peripheral interconnect device being a device that communicates with the host blade according to a peripheral interconnect data communications protocol, one of the downstream channels configured to connect to an upstream PIB segment in another BPEU.

Abstract: Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request.

Abstract: Techniques are disclosed for calculating large precision common logarithms. A common logarithm may be calculated using addition and/or subtraction of known logarithm values. Embodiments of the invention permit calculation of common logarithms of real numbers stored within character arrays, where each element of the array corresponds to a digit in the real number.

Abstract: Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.

Abstract: Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request.

Abstract: Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.

Abstract: Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.

Abstract: Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.

Abstract: Techniques are disclosed for calculating large precision common logarithms. A common logarithm may be calculated using addition and/or subtraction of known logarithm values. Embodiments of the invention permit calculation of common logarithms of real numbers stored within character arrays, where each element of the array corresponds to a digit in the real number.

Abstract: Computer peripheral expansion apparatus, methods of operation, and computer program products including blade peripheral expansion units (‘BPEUs’), each BPEU including a peripheral interconnect multiplexer coupled for peripheral interconnect data communications through an upstream peripheral interconnect bus (‘PIB’) segment to a host blade, the upstream PIB segment fanned out by the multiplexer into two or more peripheral downstream interconnect channels, the multiplexer connecting the upstream PIB segment to only one of the downstream channels at a time; and the two or more downstream peripheral interconnect channels, at least one of the downstream channels connected to at least one peripheral interconnect device (‘PID’) in the BPEU, the peripheral interconnect device being a device that communicates with the host blade according to a peripheral interconnect data communications protocol, one of the downstream channels configured to connect to an upstream PIB segment in another BPEU.

Abstract: Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.

Abstract: Methods, apparatus, and computer program products are disclosed for communicating with error checking to a device capable of operating according to an address prefix serial bus protocol that includes identifying whether the device supports error checking, and if the device supports error checking: setting the device in an error checking mode and sending a message with error checking data to the device. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include performing an error checking operation on the message to obtain error checking data. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include retrieving the device's error checking capability from a device table.

Abstract: A system and method for implementing a cable system is disclosed. The system includes a paddle card system that includes a card, and a circuit coupled to the card and configured to couple to a server system node. The circuit indicates when the card is properly seated when the card is plugged into the server system node. As a result, errors due to the paddle card system being improperly seated are minimized.

Abstract: Methods, apparatus, and computer program products are disclosed for communicating with error checking to a device capable of operating according to an address prefix serial bus protocol that includes identifying whether the device supports error checking, and if the device supports error checking: setting the device in an error checking mode and sending a message with error checking data to the device. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include performing an error checking operation on the message to obtain error checking data. Communicating with error checking to a device capable of operating according to an address prefix serial bus protocol may include retrieving the device's error checking capability from a device table.

Abstract: A system and method for managing a cable in a server system. The system includes a first paddle card coupled to a first end of the cable and a first light emitting diode (LED) coupled to the first paddle card. The first LED turns on to facilitate a user in locating the first end of the cable. The system also includes a second paddle card coupled to a second end of the cable and a second LED coupled to the second paddle card. The second LED turns on to facilitate the user in locating the second end of the cable. As a result, the ends of the cable can be conveniently and reliably located in a server system having multiple identical cables.

Abstract: An apparatus, system, and method are disclosed for assessing error over a communication link. The apparatus for assessing error is provided with a logic unit containing a plurality of modules configured to execute the necessary steps of creating one or more test packets, determining an amount of test packets to send over a communication link to a receiving node, sending a plurality of test packets over the communication link to a receiving node, interspersing test packets throughout a plurality of data packets such that the receiving node is able to continually process the data packets, and checking test packets received by the receiving node for errors.

Abstract: A redundant communication system and method for providing data communication between a first computing node and a second computing node. A transmitter is provided as part of the first computing node. A receiver is provided as part of the second computing node. A first signal line carries a first data signal. The first signal line electrically couples the transmitter with the receiver. A second signal line carries a second data signal redundant to the first signal. The second signal line electrically couples the transmitter with the receiver. The receiver evaluates the first data signal to determine the presence of an error and the second node uses the second data signal if an error is detected in the first data signal.

Abstract: An apparatus, system, and method are disclosed for automatically detecting a cable configuration. The apparatus for automatically detecting a cable configuration is provided with a logic unit containing a plurality of modules configured to functionally execute the necessary steps of storing a unique cable identifier, reading the unique cable identifier stored by a storage module, and communicating cable configuration derived from the unique cable identifier to a remote configuration manager. Beneficially, such an apparatus, system, and method will improve network reliability and significantly reduce configuration troubleshooting time. Additionally, such an apparatus, system, and method may be retrofitted into existing systems without prohibitively increasing costs or adversely affecting performance characteristics of the system.