Patents by Inventor Grace Yang

Grace Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260245147
    Abstract: Aspects described herein relate to display of data elements of high-volume, high-speed data on limited display screens. The method comprises acquiring information associated with a plurality of option products for a specific underlying asset, the information including, for each option product, information on an expiration date and information on a strike price for the specific underlying asset on the expiration date, generating a first chart in which the information associated with the plurality of option products is mapped, and outputting the generated first chart as at least part of a user interface, wherein a first axis of the first chart represents time information on the expiration dates of the plurality of option products, and a second axis of the first chart represents information on the strike prices of the specific underlying asset associated with the plurality of option products.
    Type: Application
    Filed: October 2, 2025
    Publication date: August 20, 2026
    Inventors: Jihoon Lim, Kunsup Song, Grace Yang
  • Publication number: 20260245148
    Abstract: The present disclosure relates to a method for supporting analysis, display, and/or interaction with complex real-time data items, particularly in view of the limited display functionality of some computing devices. The method comprises: acquiring information on a first chart associated with a specific data item, the information on the first chart comprising information associated with a real-time data for the specific data item; generating, based on the information on the first chart, the first chart that comprises at least one of value-fluctuation information of the specific data item for a current time and a period before the current time, or information associated with the real-time data for a period after the current time, and outputting the first chart as at least part of a user interface.
    Type: Application
    Filed: September 18, 2025
    Publication date: August 20, 2026
    Inventors: Jihoon Lim, Kunsup Song, Grace Yang
  • Publication number: 20260111978
    Abstract: A method includes: storing a patent and a file history of the patent in a data storage, collecting, labeling, and storing documentation relating to the patent in the data storage, for each chunk of the documentation, storing a vector embedding and a related chunk in a vector data structure, generating, with a language model, a version of claim constructions of the patent and a summary of the patent using the patent and the file history, creating a vector embedding for each limitation of the version of the claim constructions, identifying the vector embeddings stored in the vector data structure having the closest matches, retrieving, from the vector data structure, the chunks of documentation associated with the vector embeddings having the closest matches, and generating a claim chart using the language model based on the version of the claim constructions and the chunks of documentation associated with the closet matches.
    Type: Application
    Filed: October 23, 2025
    Publication date: April 23, 2026
    Inventors: Fei-Yang Jen, Paul Lee, Nelson Tang, Hoon Kang, Grace Yang, Yu Chuan Jason Tseng
  • Patent number: 6543128
    Abstract: A ball grid array package comprises a substrate having a first surface and a second surface, a chip, an insulating material, and a solder ball. The surface of the substrate comprises ball pads, conducting traces, and solder masks wherein the conducting traces are disposed in between the adjacent ball pads, and are covered by the solder mask, in addition, a portion of each of the ball pads is also covered by the solder mask. The solder mask includes an opening positioned in the area corresponding to the ball pads wherein the opening exposes a portion of the surface the ball pad and a portion of the side wall of the ball pad. The chip is disposed on the second surface of the substrate, and is sealed and encapsulated by the insulated material. The solder balls are disposed on the first surface of the substrate, and are positioned at the openings of the ball pads.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: April 8, 2003
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Grace Yang
  • Publication number: 20020111054
    Abstract: A ball grid array package comprises a substrate having a first surface and a second surface, a chip, an insulating material, and a solder ball. The surface of the substrate comprises ball pads, conducting traces, and solder masks wherein the conducting traces are disposed in between the adjacent ball pads, and are covered by the solder mask, in addition, a portion of each of the ball pads is also covered by the solder mask. The solder mask includes an opening positioned in the area corresponding to the ball pads wherein the opening exposes a portion of the surface the ball pad and a portion of the side wall of the ball pad. The chip is disposed on the second surface of the substrate, and is sealed and encapsulated by the insulated material. The solder balls are disposed on the first surface of the substrate, and are positioned at the openings of the ball pads.
    Type: Application
    Filed: April 11, 2002
    Publication date: August 15, 2002
    Inventors: Chien-Ping Huang, Grace Yang
  • Publication number: 20020074312
    Abstract: The present disclosure pertains to a post-etch treatment which is performed after a dielectric etch process. Using the method of the invention, byproducts formed on the sidewalls of contact vias during the dielectric etch process can be removed efficiently. The method of the invention also reduces or eliminates the problem of polymer accumulation on process chamber surfaces. Typically, after the etch of a dielectric material to define pattern or interconnect filling spaces, a series of post-etch treatment steps is performed to remove residues remaining on the wafer after the dielectric etch process. According to the method of the present invention, a post-etch treatment method including one or more steps is performed after the dielectric etch process, preferably within the same processing chamber in which the dielectric etch process was performed.
    Type: Application
    Filed: February 21, 2002
    Publication date: June 20, 2002
    Inventors: Eric Ou-Yang, Grace Yang, Lin Ye, Robert Wu, Ben Chen, Stefan Jenq
  • Patent number: 6396707
    Abstract: A ball grid array package comprises a substrate having a first surface and a second surface, a chip, an insulating material, and a solder ball. The surface of the substrate comprises ball pads, conducting traces, and solder masks wherein the conducting traces are disposed in between the adjacent ball pads, and are covered by the solder mask, in addition, a portion of each of the ball pads is also covered by the solder mask. The solder mask includes an opening positioned in the area corresponding to the ball pads wherein the opening exposes a portion of the surface the ball pad and a portion of the side wall of the ball pad. The chip is disposed on the second surface of the substrate, and is sealed and encapsulated by the insulated material. The solder balls are disposed on the first surface of the substrate, and are positioned at the openings of the ball pads.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: May 28, 2002
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Grace Yang